Mcb Clocking Considerations; Pci; Gtp Transceivers; Gtp Transceiver Pin Planning Considerations - Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

All supported MCB interfaces (with the exception of LPDDR) require the use of the V
pins to provide the appropriate voltage reference. Therefore, for all memory interfaces
(except LPDDR), the multi-function pins with V
the I/O bank that contains an MCB.

MCB Clocking Considerations

When designing with MCBs, examine the MIG generated pin assignment and note the
GCLK pins that are used, since they are not available for general use.
Larger devices have two additional I/O banks, banks 4 and 5. When two MCBs are both
used on the same side of the device in a design (example: the MCBs in I/O banks 1 and 5),
they must be clocked with the same BUFPLL_MCB. The two MCBs share a common clock
rate. See Chapter 3 of the Spartan-6 FPGA Memory Controller User Guide for recommended
PLL and BUFPLL_MCB usage.

PCI

To generate valid pin placements for PCI, use the Core Generator tool. The IRDY and
TRDY pins are used for PCI core designs and are multi-functional with the GCLK pins.
Whenever a PCI core is used in a particular I/O bank, the IRDY and TRDY pins in that
bank will not be available to use for GCLK.

GTP Transceivers

GTP Transceiver Pin Planning Considerations

Spartan-6 devices that contain GTP transceiver pins must be correctly connected,
regardless of whether any GTP transceivers are used. See the board design guideline
(chapter 5) in UG386: Spartan-6 FPGA GTP Transceivers User Guide for further details.
Use GTP0 when only using one GTP transceiver of a GTPA1_DUAL transceiver pair and
ensure that the incoming reference clock is connected to the REFCLK pins on GTP0. The
REFCLK for GTP1 will not be powered. Tie all unused GTP transceiver pins to ground,
including the power pins.
Do not share the GTP transceiver's REFCLKs from the top half of the device with the
bottom half REFCLKs. The GTP transceivers located on the top half of the device (I/O
bank 0) are independent of the GTP transceivers located on the bottom half of the device
(I/O bank 2), and must have their own REFCLKs connected to them.
For the best signal integrity, avoid assigning user I/O pins to SelectIO locations directly
adjacent to GTP transceiver power or data pins. Diagonally adjacent pins are acceptable.
Transceiver speeds require very specific board-level termination. Recommended
terminations and signal conditioning are outlined in the BUFIO2 Input Conflicts for SDR
Data Rates and BUFIO2 Input Conflicts for DDR Data Rates tables (Chapter 1) of the Spartan-6
FPGA Clocking Resources User Guide.
Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
REF
www.xilinx.com
will not be available as user I/O within
PCI
REF
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