Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual page 21

Because the voltage level of V
manifested as changing current demand. The PDS must accommodate these variances of
current draw with as little change as possible in the power-supply voltage.
When the current draw in a device changes, the PDS cannot respond to that change
instantaneously. As a consequence, the voltage at the device changes for a brief period
before the PDS responds. Two main causes for this PDS lag correspond to the two major
PDS components: the voltage regulator and decoupling capacitors.
The first major component of the PDS is the voltage regulator. The voltage regulator
observes its output voltage and adjusts the amount of current it is supplying to keep the
output voltage constant. Most common voltage regulators make this adjustment in
milliseconds to microseconds. Voltage regulators effectively maintain the output voltage
for events at all frequencies from DC to a few hundred kHz, depending on the regulator
(some are effective at regulating in the low MHz). For transient events that occur at
frequencies above this range, there is a time lag before the voltage regulator responds to
the new current demand level.
For example, if the device's current demand increases in a few hundred picoseconds, the
voltage at the device sags by some amount until the voltage regulator can adjust to the
new, higher level of required current. This lag can last from microseconds to milliseconds.
A second component is needed to substitute for the regulator during this time, preventing
the voltage from sagging.
This second major PDS component is the decoupling capacitor (also known as a bypass
capacitor). The decoupling capacitor works as the device's local energy storage. The
capacitor cannot provide DC power because it stores only a small amount of energy
(voltage regulator provides DC power). This local energy storage should respond very
quickly to changing current demands. The capacitors effectively maintain power-supply
voltage at frequencies from hundreds of kHz to hundreds of MHz (in the milliseconds to
nanoseconds range). Decoupling capacitors are not useful for events occurring above or
below this range.
For example, if current demand in the device increases in a few picoseconds, the voltage at
the device sags by some amount until the capacitors can supply extra charge to the device.
If current demand in the device maintains this new level for many milliseconds, the
voltage-regulator circuit, operating in parallel with the decoupling capacitors, replaces the
capacitors by changing its output to supply this new level of current.
Figure 2-3
capacitors, and the active device being powered (FPGA).
X-Ref Target - Figure 2-3
Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
shows the major PDS components: the voltage regulator, the decoupling
+
Voltage
V
Regulator
Figure 2-3: Simplified PDS Circuit
www.xilinx.com
for a device is fixed, changing power demands are
CC
L
REGULATOR
Basic PDS Principles
L
DECOUPLING
FPGA
C
DECOUPLING
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