Transmission Lines - Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

package pin or ball pitch (1.0 mm for FG packages) defines the land pad layout. The
minimum surface feature sizes of current PCB technology define the via arrangement in
the area under the device. Minimum via diameters and keep-out areas around those vias are
defined by the PCB manufacturer. These diameters limit the amount of space available
in-between vias for routing of signals in and out of the via array underneath the device.
These diameters define the maximum trace width in these breakout traces. PCB
manufacturing limits constrain the minimum trace width and minimum spacing.
The total number of PCB layers necessary to accommodate an FPGA is defined by the
number of signal layers and the number of plane layers.
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PCBs for larger FPGAs can range from 4 to 22 layers.
System compliance often defines the total thickness of the board. Along with the number
of board layers, this defines the maximum layer thickness, and therefore, the spacing in the
Z direction of signal and plane layers to other signal and plane layers. Z-direction spacing
of signal trace layers to other signal trace layers affects crosstalk. Z-direction spacing of
signal trace layers to reference plane layers affects signal trace impedance. Z-direction
spacing of plane layers to other plane layers affects power system parasitic inductance.
Z-direction spacing of signal trace layers to reference plane layers (defined by total board
thickness and number of board layers) is a defining factor in trace impedance.Trace width
(defined by FPGA package ball pitch and PCB via manufacturing constraints) is another
factor in trace impedance. A designer often has little control over trace impedance in area
of the via array beneath the FPGA. When traces escape the via array, their width can
change to the width of the target impedance (usually 50Ω single-ended).
Decoupling capacitor placement and discrete termination resistor placement are other
areas of trade-off optimization. DFM constraints often define a keep-out area around the
perimeter of the FPGA (device footprint) where no discrete components can be placed. The
purpose of the keep-out area is to allow room for assembly and rework where necessary.
For this reason, the area just outside the keep-out area is one where components compete
for placement. It is up to the PCB designer to determine the high priority components.
Decoupling capacitor placement constraints are described in
Distribution
through signal integrity simulation, using IBIS or SPICE.

Transmission Lines

The combination of a signal trace and a reference plane forms a transmission line. All I/O
signals in a PCB system travel through transmission lines.
For single-ended I/O interfaces, both the signal trace and the reference plane are necessary
to transmit a signal from one place to another on the PCB. For differential I/O interfaces,
the transmission line is formed by the combination of two traces and a reference plane.
While the presence of a reference plane is not strictly necessary in the case of differential
signals, it is necessary for practical implementation of differential traces in PCBs.
Good signal integrity in a PCB system is dependent on having transmission lines with
controlled impedance. Impedance is determined by the geometry of the traces and the
Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
The number of signal layers is defined by the number of I/O signal traces routed in
and out of an FPGA package (usually following the total User I/O count of the
package for array packages).
The number of plane layers is defined by the number of power and ground plane
layers necessary to bring power to the FPGA and to provide references and isolation
for signal layers.
System. Termination resistor placement constraints must be determined
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Transmission Lines
Chapter 2, Power
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