Omron CV500 Installation Manual page 26

Improved Specifications
1-9-2 Version-1 CPUs
PT Link Function
EEPROM Writes
New Command
Faster Host Links
Faster Searches
1-9-3 Version-2 CVM1 PCs
3. The operation of Completion Flags for timers has been changed so that the
Completion Flag for a timer turns ON only when the timer instruction is
executed with a PV of 0000 and not when the timer's PV is refreshed to a PV
value of 0000, as was previously done.
Only the timing of the activation of the Completion Flag has been changed,
and the timer's PV is still refreshed at the same times (i.e., when the timer
instruction is executed, at the end of user program execution, and every
80 ms if the cycle time exceeds 80 ms).
4. The READ(190) (I/O READ) and WRIT(191) (I/O WRITE) instructions have
been improved so that they can be used for Special I/O Units on Slave
Racks under the following conditions.
a) The lot number of the Remote I/O Master Unit and Remote I/O Slave Unit
must be the same as or latter than the following.
01 X 2
b) The DIP switch on the Remote I/O Slave Unit must be set to "54MH."
c) The Special I/O Unit must be one of the following: AD101, CT012,
CT021, CT041, ASC04, IDS01-V1, IDS02, IDS21, IDS22, or LDP01-V1.
(The NC221-E, NC222, CP131, and FZ001 cannot be mounted to Slave
Racks.)
CV-series CPUs were changed to version 1 from December 1993. The new
model numbers are as follows: CVM1-CPU01-EV1, CVM1-CPU11-EV1,
CV500-CPU-EV1, CV1000-CPU-EV1, and CV2000-CPU-EV1. (Of these, all
CVM1 CPUs were changed to version 2 from December 1994; refer to the next
sections for details.)
The following additions and improvements were made to create the version-1
CPUs.
The host link interface on the CPU can be used to connect directly to Program-
mable Terminals (PTs) to create high-speed data links. To use the PT links, turn
ON pin 3 of the DIP switch on the CPU. Pin 3 must be turned OFF for host link
connections.
With the new CPUs, you can write to EEPROM Memory Cards mounted to the
CPU by using the file write operation from a Peripheral Device. A Memory Card
Writer is no longer required for this write operation. Writing is possible in PRO-
GRAM mode only.
A new I/O REGISTER command (QQ) has been added so that words from differ-
ent data areas can be read at the same time.
The communications response time for the built-in host link interface on the CPU
has been improved by a factor of approximately 1.2.
The search speed from Peripheral Devices for instructions and operands has
been nearly doubled.
CVM1 CPUs were changed to version 2 and a new CPU was added from De-
cember 1994. The new model numbers are as follows: CVM1-CPU01-EV2,
CVM1-CPU11-EV2, and CVM1-CPU21-EV2.
1992
October (Y: November; Z: December)
1st
Section 1-9
13