External Event / General Event / General Power Management / General Purpose Open Collector - AMD SP5100 Data Book

44409 Rev. 1.70 October 10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3/IMC_GPIO13
SDA3/IMC_GPIO14
SMBALERT#/
THRMTRIP#/
GEVENT2#
Notes: (1) SDA1 and SCL1 SMBus interface is the secondary SMBUS in the S5 power domain, and should be
connected to devices that reside in the S5 power domain.
(2) There are only two SMBus controllers. The SCL1/SDA1 pair is controlled by SMBus controller 1.
SCL0/SDA0, SCL2/SDA2, and SCL3/SDA3 are multiplexed pins that are all controlled by SMBus controller
0, and only 1 pair of those pins can be active at any time.
7.14 External Event / General Event / General Power Management /
General Purpose Open Collector
The EXTEVENT/GEVENT/GPM/GPOC pins of the SP5100 are multiplexed with other functions. For
information on how to configure the EXTEVENT/GEVENT/GPM/ GPOC pins for the desired functions,
see the AMD SP5100 Register Reference Guide.
The table below lists all the EXTEVENT/GEVENT/GPM/GPOC pins on the SP5100. The Default Type
column shows the state of the pin (default function) after de-assertion of the PCI host bus reset
(A_RST#), which happens after power up or after system reset. Signals that are in input state after reset
will be tri-state (TS) if they do not have any internal PU (pull-up) or PD (pull-down). For pins that have PU
or PD internally, their states after reset will depend on the PU or PD: for signals with PU, the state will be
HIGH and for signals with PD the state will be LOW. The PU and PD shown are enabled by default after
PCI Reset and can be disabled by System BIOS.
Abbreviations: PU = pull-up, PD = pull-down, OD = open drain, I/O = Input/Output, TS = tri-state
Ball Name
(Default Function Type
in Blue)
USB_OC0#/
I/O
GPM0#
USB_OC1#/
I/O
GPM1#
USB_OC2#/
I/O
GPM2#
I/OD S5_3.3V (5-V Tolerance) SMBus Clock 2/IMC GPIO11
I/OD S5_3.3V (5-V Tolerance) SMBus Data 2/IMC GPIO12
I/OD 0.8-V threshold,
S5_3.3V domain
I/OD 0.8-V threshold,
S5_3.3V domain
I/O S5_3.3V
Internal
Resistor
Voltage and
Domain
(Default in
10-kΩ PU
3.3V_S5
10-kΩ PD
10-kΩ PU
3.3V_S5
10-kΩ PD
10-kΩ PU
3.3V_S5
10-kΩ PD
Signal Description
Note: Pin type is I/O when the pin is configured as
GPIO.
Note: Pin type is I/O when the pin is configured as
GPIO.
SMBus Clock 3/IMC GPIO13
Note: Pin type is I/O when the pin is configured as
GPIO.
SMBus Data 3/IMC GPIO14
Note: Pin type is I/O when the pin is configured as
GPIO.
SMBus Alert# / Thermal Trip / General Event 2
SM Bus Alert: This signal is used to wake the system
or generate an SMI#. If not used for SMBALERT#, it
can be used for thermal trip or as a GEVENT.
Default
Type
(Default Functional Description
State in
Blue)
Blue)
USB Over Current 0/
Input
GPM 0
USB Over Current 1/
Input
GPM 1
USB Over Current 2/
Input
GPM 2
AMD SP5100 Databook
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