Table of Contents
Advertisement
Revision History
Date
Oct 2010
Revision
Description
1.70
First release of the public version. Changes from the latest released NDA
version include:
•
Updated Table 11-3, "DC Characteristics for Interface on the SP5100":
Corrected VIL minimum value to -0.5V for CPU signals, RSMRST#, and
SBPWRGD; filled in ILI values for NB-ALLOW_LDTSTP, RSMRST#, and
SBPWRGD; corrected condition for GPIO/IMC_GPIO and IDE pins' VOH
to IOH=-8.0mA.
•
Updated Table 14-5, "List of Pins on the SP5100 XOR Chain and the
Order of Connection": Corrected pin names at XOR# 113 and 114 to
USB_FSD13P and USB_FSD12P.
•
Updated Section 7.12, "Northbridge / Power Management Interface":
Revised description for WAKE#/GEVENT8#.
•
Updated Section 7.13, "SMBus Interface/General Purpose Open
Controller": Removed references to ASF, as the feature is no longer
supported; SCL1/ SDA1 interface is now used as secondary SMBUS in
the S5 power domain.
Advertisement
Table of Contents
