Sp5100 Strap Information; Figure 4-1: Straps Capture; Figure 4-2: Type Ii Straps Capture Timing - AMD SP5100 Data Book

AMD SP5100 Databook

4 SP5100 Strap Information

There are two kinds of strap-latching logic, Type I and Type II. Type I straps will be latched on G3 to S5
transition on rising edge of RSMRST#. Type II straps are latched on S5 to S0 transition after rising edge
of PWR_GOOD assertion.
Straps I
Capture
S5_1.2V
RsmRst #
STRAPs ( board)
VDD
PwrGood
Undefined
Straps Type I
Straps Type II
S5 3.3V /S5 1.2V
POWER GOOD
Timing is system
dependent
Undefined
PCI_RST#
20
Don' t care
Straps I

Figure 4-1: Straps Capture

~31 ms
25 ms
PCI Clock signal is tristate can be
High or Low
PCI reset asserted
PCI device in Reset

Figure 4-2: Type II Straps Capture timing

SP5100 Strap Information
44409 Rev. 1.70 October 10
Straps II
Straps II
Capture
Straps Type I
Straps Type II
T1
PCI Clock PCI Clock stable 33 MHz
Strap signal
must be stable
and at valid
state
PCI device will
functional here