Signal Description; Cpu Interface; Lpc Interface - AMD SP5100 Data Book

Table of Contents

Advertisement

44409 Rev. 1.70 October 10

7 Signal Description

7.1

CPU Interface

Pin name
Type
LDT_PG
OD
LDT_RST#
OD
LDT_STP#
OD
PROCHOT#
I
7.2

LPC Interface

Pin Name
GA20IN
KBRST#
LAD[3:0]
LPCCLK0
LPCCLK1
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/
GPIO68
LPC_SMI#/EXTEVNT1#
SERIRQ
Voltage
Functional Description
S5_3.3V
LDT Power Good
LDT Reset#
LDT Reset#: Reset signal to the CPU.
Assertion of LDT_RST# causes the CPU to transition into a low power
state and to de-assert MEMCLKEA/B and assert MEMREST_L.
Assertion of LDT_RST# takes place sometime after SB PWR_GOOD
S5_3.3V
has been de-asserted.
De-assertion of LDT_RST# allows MEMRESET_L to be de-asserted
and MEMCLK to be enabled. De-assertion of LDT_RST# takes place
sometime after SB PWR_GOOD has been asserted.
S5_3.3V
Assertion of LDTSTOP# on the CPU causes it to enter C3, or
S1/S2/S3/S4/S5. Assertion takes place: (a) for S1/S2/S3/S4/S5: after
SUS_STAT# is asserted; (b) for C3: after the STPGNT message is
received by the system.
De-assertion of LDTSTOP_L causes the CPU to return to C0 or S0
state. De-assertion takes place following a wake-up event:
(a) in S1: at an interval (programmed by an SB register) after de-
assertion of CPU_STP#;
(b) in S2: after SLP_S2 is de-asserted;
(c) in S3/S4/S5: after SB PWR_GOOD is asserted;
(d) in C3: at an interval (programmed by an SB register)
Starting with RS78x, NB will control the LDT_STP# during C state.
0.8-V
Processor Hot: Similar to TALERT#. When it is asserted, it can
threshold,
generate SCI or SMI to OS/BIOS.
S5_3.3V
domain
Type
Voltage
I
3.3 V
I
3.3 V
I/O
S5_3.3 V
O
S5_3.3 V
O
S5_3.3 V
O
S5_3.3 V
I
S5_3.3 V
I/O
3.3 V
I
S5_3.3 V
I/O
3.3 V
Signal Description
Functional Description
A20 Gate Input from SIO
Keyboard reset#
Multiplexed Command/Address/Data [3:0]
LPCCLK 0 (See Note)
LPCCLK 1 (See Note)
Frame. Indicates start of a new cycle or termination of
broken cycle.
Encoded DMA/Bus Master Request 0
Encoded DMA/Bus Master Request 1 / PCI bus Grant 5
from SP5100 / GPIO 68
LPC SMI / External Event 1
Serial IRQ
AMD SP5100 Databook
33

Advertisement

Table of Contents
loading

Table of Contents