X 1 Lane Interface For General Purpose External Devices; Miscellaneous Pci Express® Signals; Clock Interface; Table 3-6 Clock Interface - AMD RX881 Data Book

3.4.3

6 x 1 Lane Interface for General Purpose External Devices

Note: The widths of the A-Link Express II interface and the general purpose links for external devices are configured
through the programmable strap GPPSB_LINK_CONFIG, which is programmed through RX881's registers. See the
RS880 ASIC Family Register Reference Guide, order# 46412, and the RS880 ASIC Family Register Programming
Requirements, order# 46141, for details.
Table 3-4 6 x 1 Lane PCI Express
Pin Name
GPP_TX[5:0]P,
GPP_TX[5:0]N
GPP_RX[5:0]P,
GPP_RX[5:0]N
3.4.4 Miscellaneous PCI Express
Table 3-5 PCI Express
Pin Name
PCE_CALRN
PCE_CALRP
3.5

Clock Interface

Table 3-6 Clock Interface

Pin Name
HT_REFCLKP,
HT_REFCLKN
GFX_REFCLKP,
GFX_REFCLKN
GPPSB_REFCLKP,
GPPSB_REFCLKN
GPP_REFCLKP,
GPP_REFCLKN
REFCLK_P,
REFCLK_N
*Note: Internal clock mode is only available when using an SB8xx Southbridge. Use of the internal clock generator function is subject to
characterization with actual RX881 and SB8xx devices
46136 AMD RX881 Databook 1.40
3-6
®
Interface for General Purpose External Devices
Power Ground
Type
Domain Domain
O VDDPCIE VSSAPCIE
I VDDPCIE VSSAPCIE
®
Signals
®
Interface for Miscellaneous PCI Express
Power Ground
Type
Domain Domain
Other VDDPCIE VSSAPCIE
Other VDDPCIE VSSAPCIE
Power Ground
Type
Domain Domain
VDDA18H
I VSSAHT
TPLL
I/O VDDPCIE VSSAPCIE
I VDDPCIE VSSAPCIE
O VDDPCIE VSSAPCIE
I VDD33 VSS
Integrated
Termination Functional Description
50 between Transmit Data Differential Pairs. Connect to external connectors on
complements the motherboard for add-in card or ExpressCard support.
50 between Receive Data Differential Pairs. Connect to external connectors on
complements the motherboard for add-in card or ExpressCard support.
®
Signals
Functional Description
RX Impedance Calibration. Connect to VDDPCIE on the motherboard with an
external resistor of an appropriate value.
TX Impedance Calibration. Connect to GND on the motherboard with an external
resistor of an appropriate value.
Integrated
Functional Description
Termination
HyperTransport™ 100MHz reference clock differential pair
External clock mode: Input from external clock source, as a
– reference clock for the HyperTransport interface.
Internal clock mode*: Input from the SB8xx Southbridge, as a
reference clock for the HyperTransport interface.
Clock Differential Pair for external graphics.
External clock mode: Input from the external clock generator, as a
50 between reference clock for external graphics.
complements Internal clock mode*: Not used. Pull down following instructions in
the RS880-Series IGP Motherboard Schematic Review
Checklist.
Clock Differential Pair for Southbridge and general purpose PCIe
devices.
50 between External clock mode: Input from the external clock generator, as a
complements reference clock for A-Link Express II and general purpose PCIe.
Internal clock mode*: Input from the SB8xx Southbridge, as a
reference clock for A-Link II and general purpose PCIe.
Clock Differential Pair for general purpose PCIe devices.
External clock mode: Not used. Can be left unconnected, or
50 between
connected to the external clock generator for maintaining system
complements
compatibility with the RX881.
Internal clock mode*: Output to a GPP device slot as a GPP clock.
Do not connect.
–
Clock Interface
© 2011 Advanced Micro Devices, Inc.
®
Proprietary