Analog Devices ADuC7026 Application Notes page 8

AN-744
Table 3. Pin Functions for Digital I/O Connector J2
Pin No. Pin Description
J2-1 DGND
J2-2 P4.5
AD13/PLAO[13]
J2-3 P4.4
AD12/PLAO[12]
J2-4 P4.3
AD/11PLAO[11]
J2-5 P4.2
AD10/PLAO[10]
J2-6 P1.0
T1/SIN/SCL0/PLAI[0]
J2-7 P1.1
SOUT/SDA0/PLAI[1]
J2-8 P1.2
RTS/SCL1/PLAI[2]
J2-9 P1.3
CTS/SDA1/PLAI[3]
J2-10 P1.4
IRQ2/RI/CLK/PLAI[4]
J2-11 P1.5
IRQ3/DCD/MISO/PLAI[5]
J2-12 P4.1
AD9/PLAO[9]
J2-13 P4.0
AD8/PLAO[8]
J2-14 P1.6
DSR/MOSI/PLAI[6]
J2-15 P1.7
DTR/CSL/PLAO[0]
J2-16 P2.2
PWM0 /RS/PLAO[7]
L
J2-17 P2.1
PWM0 /WS/PLAO[6]
H
J2-18 P2.7
PWM1 /MS3
L
J2-19 P3.7
PWM /AD7/PLAI[15]
SYNC
J2-20 P3.6
PWM /AD6/PLAI[14]
TRIP
J2-21 P0.7
ECLK/XCLK/SIN/PLAO[4]
Pin No. Pin Description
J2-22 P2.0
CONV
J2-23 P0.5
IRQ1/ADC
J2-24 P0.4
IRQ0/PWM
J2-25 P3.5
PWM2
J2-26 P3.4
PWM2
J2-27 P2.6
PWM1
J2-28 P2.5
PWM0
J2-29 P0.3
TRST/A16/ADC
J2-30 P2.4
PWM0
J2-31 P3.3
PWM1
J2-32 P3.2
PWM1
J2-33 P3.1
PWM0
J2-34 P3.0
PWM0
J2-35 P0.2
PWM2
J2-36 P0.6
T1/MRST/AE/PLAO[3]
J2-37 P0.0
CMP/MS2/PLAI[7]
J2-38 P4.7
AD15/PLAO[15]
J2-39 P4.6
AD14/PLAO[14]
J2-40 P2.3
AE
J2-41 P0.1
PWM2
J2-42 DGND
Rev. A | Page 8 of 16
/SOUT/PLAO[5]
START
/MS0/PLAO[2]
BUSY
/MS1/PLAO[1]
TRIP
/AD5/PLAI[13]
L
/AD4/PLAI[12]
H
/MS2
H
/MS1
L
BUSY
/MS0
H
/AD3/PLAI[11]
L
/AD2/PLAI[10]
H
/AD1/PLAI[9]
L
/AD0/PLAI[8]
H
/BHE
L
/BLE
H