Schematic Diagrams
Processor 8/11
1.05S_VCCST
D
Sheet 9 of 42
CAD Note: H_CPU_SVIDALRT_R_N
Place the PU resistors close to CPU
Processor 8/11
C
B
A
B - 10 Processor 8/11
5
4
SVID Signals
R474
75_04
H_CPU_SVIDALRT#
PJ11
H_CPU_SVIDDAT
V_VCCDDQ_R
R471
110_1%_04
1
2
V_VCCDDQ
*OPEN-5mm
VCCIN
R91
100_04
R437
*0_04
VCC_SENSE
36
VCC_SENSE
11,36
VSS_SENSE
R412
0_06
VCCIO_OUT
R442
R94
0_04
VCCIOA_OUT
100_04
R473
43.2_1%_04
H_CPU_SVIDALRT_R_N
36
H_CPU_SVIDALRT#
R482
*10mil_short
H_CPU_SVIDCLK_R
36
H_CPU_SVIDCLK
H_CPU_SVIDDAT_R
R470
*10mil_short
36
H_CPU_SVIDDAT
R416
0_04
2
H_VCCST_PW RGD
R81
0_04
36
H_VR_ENABLE
H_VR_READY
R423
0_04
PW R_DEBUG_N
R102
150_1%_04
1.05S_VCCST
RESISTOR STUFFING OPTIONS ARE
R103
PROVIDED FOR TESTING PURPOSES
*10K_04
1.05VS
1.05S_VCCST
1.05S_VCCST
R158
0_04
VCCIN
C152
22u_6.3V_X5R_08
V_VCCDDQ
4.2A
C582
+
C214
C224
C215
10u_6.3V_X5R_06
10u_6.3V_X5R_06
*10u_6.3V_X5R_06
C529
C535
C530
22u_6.3V_X5R_08
22u_6.3V_X5R_08
*22u_6.3V_X5R_08
5
4
3
32A
HSW_ULT_DDR3L
U29L
L59
C36
RSVD
VCC
J58
C40
RSVD
VCC
C44
1.4A
VCC
AH26
C48
VDDQ
VCC
AJ31
C52
VDDQ
VCC
AJ33
C56
VDDQ
VCC
AJ37
E23
VDDQ
VCC
AN33
E25
VDDQ
VCC
AP43
E27
VDDQ
VCC
AR48
E29
VDDQ
VCC
AY35
E31
VDDQ
VCC
AY40
E33
VDDQ
VCC
AY44
E35
VDDQ
VCC
AY50
E37
VDDQ
VCC
E39
VCC
F59
E41
VCC
VCC
N58
E43
RSVD
VCC
AC58
E45
RSVD
VCC
E47
VCC
E63
E49
VCC_SENSE
VCC
AB23
E51
RSVD
VCC
A59
E53
VCCIO_OUT
VCC
E20
E55
VCCIOA_OUT
VCC
AD23
E57
RSVD
VCC
AA23
F24
RSVD
VCC
AE59
F28
RSVD
VCC
F32
VCC
L62
F36
VIDALERT
VCC
N63
HSW ULT POWER
F40
VIDSCLK
VCC
L63
F44
VIDSOUT
VCC
B59
F48
VCCST_PWRGD
VCC
F60
F52
VR_EN
VCC
C59
F56
VR_READY
VCC
G23
VCC
D63
G25
VSS
VCC
H59
G27
PWR_DEBUG
VCC
P62
G29
VSS
VCC
P60
G31
RSVD_TP
VCC
P61
G33
RSVD_TP
VCC
N59
G35
RSVD_TP
VCC
N61
G37
RSVD_TP
VCC
T59
G39
RSVD
VCC
AD60
G41
RSVD
VCC
AD59
G43
RSVD
VCC
AA59
G45
RSVD
VCC
AE60
G47
RSVD
VCC
AC59
G49
RSVD
VCC
AG58
G51
RSVD
VCC
U59
G53
RSVD
VCC
V59
G55
RSVD
VCC
G57
VCC
AC22
H23
VCCST
VCC
AE22
J23
VCCST
VCC
AE23
K23
VCCST
VCC
K57
VCC
AB57
L22
VCC
VCC
AD57
M23
VCC
VCC
AG57
M57
VCC
VCC
C24
P57
VCC
VCC
C28
U57
VCC
VCC
C32
W57
VCC
VCC
12 OF 19
C758
0.01u_50V_X7R_04
H_VR_ENABLE
R68
10K_04
H_VR_READY
R424
0_04
VR_READY 36
3
2
1
PROCESSOR CORE POWER
VCCIN
C86
C461
C140
C139
C110
C469
C460
VCCIN
C434
C76
C88
C112
C75
C72
C70
C111
C71
C433
C459
C87
C149
C77
C148
C414
VCCIN
C424
C447
+
+
V_VCCDDQ
4.2A
C580
+
C232
C231
C223
10u_6.3V_X5R_06
10u_6.3V_X5R_06
*10u_6.3V_X5R_06
C546
C545
C534
22u_6.3V_X5R_08
22u_6.3V_X5R_08
*22u_6.3V_X5R_08
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
2,7,36
1.05S_VCCST
Title
Title
Title
[09] HASWELL ULT POWER 1
[09] HASWELL ULT POWER 1
[09] HASWELL ULT POWER 1
8
VCCIO_OUT
2
VCCIOA_OUT
2,3,13,14,35,37
V_VCCDDQ
Size
Size
Size
Document Number
Document Number
Document Number
6-71-W8400-D04A
5,10,32
1.05VS
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
36
VCCIN
Date:
Date:
Date:
Thursday, December 18, 2014
Thursday, December 18, 2014
Thursday, December 18, 2014
Sheet
Sheet
Sheet
2
1
C413
C417
D
C468
C450
C150
C151
C
B
A
Rev
Rev
Rev
1.0
1.0
1.0
9
9
9
of
of
of
42
42
42
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