Digital Equipment HiNote VP 500 Series Service Manual page 41

Code Beeps
39
3A
3C
3D
40
42
44
46 2-1-2-3
47
48
49
4A
4C
4E
50
51
52
54
56
58 2-2-3-1
5A
5C
60
62
64
66
68
6A
6C
6E
70
72
74
76
7C
7E
80
82
84
86
88
8A
8C
90
91
POST Routine Description
Reinitialize the cache
Autosize cache
Configure advanced chipset registers
Load alternate registers with CMOS values
Set Initial CPU speed
Initialize interrupt vectors
Initialize BIOS interrupts
Check ROM copyright notice
Initialize manager for PCI Option ROMs
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
Shadow video BIOS ROM
Display copyright notice
Display CPU type and speed
Initialize EISA board
Test keyboard
Set key click if enabled
Enable keyboard
Test for unexpected interrupts
Display prompt "Press F2 to enter SETUP"
Test RAM between 512 and 640k
Test extended memory
Test extended memory address lines
Jump to UserPatch1
Configure advanced cache registers
Enable external and CPU caches
Display external cache size
Display shadow message
Display non-disposable segments
Display error messages
Check for configuration errors
Test real-time clock
Check for keyboard errors
Set up hardware interrupt vectors
Test coprocessor if present
Disable onboard I/O ports
Detect and install external RS232 ports
Detect and install external parallel ports
Re-initialize onboard I/O ports
Initialize BIOS Data Area
Initialize Extended BIOS Data Area
Initialize floppy controller
Initialize hard-disk controller
Initialize local-bus hard-disk controller
Digital HiNote VP 500 Service Guide 3–7
Troubleshooting