Advantech AIMB-584 User Manual page 73

Intel® xeon® e3/core™ i7/i5/i3 lga1150 microatx with crt/ dvi/edp/lvds/dp, 6 com, dual lan, ddr3, pcie x 16 and sataiii
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3.3.1.1
PCI Express Configuration
PCI Express Clock Gating [ Enabled ]
Enable or Disable PCI Express clock gating for each port.
DMI Link ASPM Control [ Enabled ]
The control of Active State Power Management on both NB side and SB side of
the DMI Link.
DMI Link Extended Synch Control [ Disabled ]
The control of Extended Synch on SB side of the DMI Link.
PCIe-USB Glitch W/A [ Disabled ]
PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG Port.
PCIE Root Port Function Swapping [ Disabled ]
Enable or disable PCI Express PCI Express Root Port Function Swapping.
Subtractive Decode [ Disabled ]
Enable or disable PCI Express Subtractive Decode.
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AIMB-584 User Manual

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