Dma I/O Address Map - IBM NetWista A60 Type 6838 User Manual

Table 2. I/O address map (continued)
Address range (hex)
03F7 (Write)
03F7, bit 7
03F7, bits 6:0
03F8 – 03FF
0400 – 047F
0480 – 048F
0490 – 0CF7
0CF8 – 0CFB
0CFC – 0CFF
LPTn + 400h
OCF9
0D00 – FFFF

DMA I/O address map

Table 3. DMA I/O address map
Address (hex) Description
0000 Channel 0, memory address register
0001 Channel 0, transfer count register
0002 Channel 1, memory address register
0003 Channel 1, transfer count register
0004 Channel 2, memory address register
0005 Channel 2, transfer count register
0006 Channel 3, memory address register
0007 Channel 3, transfer count register
0008 Channels 0–3, read status/write command register
0009 Channels 0–3, write request register
000A Channels 0–3, write single mas register bits
000B Channels 0–3, mode register (write)
000C Channels 0–3, clear byte pointer (write)
000D Channels 0–3, master clear (write)/temp (read)
000E Channels 0-3, clear mask register (write)
000F Channels 0-3, write all mask register bits
0081 Channel 2, page table address register
0082 Channel 3, page table address register
0083 Channel 1, page table address register
0087 Channel 0, page table address register
0089 Channel 6, page table address register
Size Description
1 Diskette channel 1 command
1 bit Diskette disk change channel
7 bits Primary IDE channel status port
8 COM1
128 Available
16 DMA channel high page registers
1912 Available
4 PCI configuration address register
4 PCI configuration data register
8 ECP port, LPTn base address + hex 400
1 Turbo and reset control register
62207 Available
The following table lists resource assignments for the DMA address map. Any
addresses that are not shown are reserved.
Bits Byte pointer
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 07
00 – 02
00 – 02
00 – 07
A
00 – 07
00 – 03
00 – 03
00 – 07
00 – 07
00 – 07
00 – 07
00 – 07
Appendix C. System address maps
41