Dma I/O Address Map - IBM NetVista X40 Technical Information Manual

DMA I/O address map

Table 34. DMA I/O address map
Address (hex) Description
0000 Channel 0, Memory Address register
0001 Channel 0, Transfer Count register
0002 Channel 1, Memory Address register
0003 Channel 1, Transfer Count register
0004 Channel 2, Memory Address register
0005 Channel 2, Transfer Count register
0006 Channel 3, Memory Address register
0007 Channel 3, Transfer Count register
0008 Channels 0–3, Read Status/Write Command
register
0009 Channels 0–3, Write Request register
000A Channels 0–3, Write Single Mask register bits
000B Channels, 0–3, Mode register (write)
000C Channels 0–3, Clear byte pointer (write)
000D Channels, 0–3, Master clear (writer)/temp (read)
000E Channels 0–3, Clear Mask register (write)
000F Channels 0–3, Write All Mask register bits
0081 Channel 2, Page Table Address register
0082 Channel 3, Page Table Address register
0083 Channel 1, Page Table Address register
0087 Channel 0, Page Table Address register
0089 Channel 6, Page Table Address register
008A Channel 7, Page Table Address register
008B Channel 5, Page Table Address register
008F Channel 4, Page Table Address/Refresh register
00C0 Channel 4, Memory Address register
00C2 Channel 4, Transfer Count register
00C4 Channel 5, Memory Address register
00C6 Channel 5, Transfer Count register
00C8 Channel 6, Memory Address register
00CA Channel 6, Transfer Count register
00CC Channel 7, Memory Address register
36
Technical Information
Bits Byte pointer
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes
00–07
00–02
00–02
00–07
N/A
00–07
00–03
00–03
00–07
00–07
00–07
00–07
00–07
00–07
00–07
00–07
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes
00–15 Yes