Motorola D10 Service Manual page 63

BenQ
3.3 Power Supply circuit
B2
C2
GND
C3
BU/PWT
B1
VDDS2
C1
LT/PWL
D3
SDO/INT10n
D2
RX_MODEM
D1
TX_MODEM
F5
SD_IRDA/CLKOUT_DSP
E4
DSR_MODEM/LPG
E2
RTS_MODEM/TOUT
E3
CTS_MODEM/XF
E1
SCLK/INT1n
F4
RX_IRDA
F3
nSCS0/SCL
F2
RXIR_IRDA/X_A1
F1
TX_IRDA
G5
TXIR_IRDA/X_A4
G4
nSCS1/X_A2
G2
nEMU1
G3
nEMU0
G1
nRESPWRON
H1
TCK
H3
TMS
H2
TDO
H4
TDI
H5
nBSCAN
J1
EN_LMM_PWR/X_IOSTRB
J2
IO0/TPU_WAIT
J3
GND
J4 IO1/TPU_IDLE
K1 ADD0
K3
ADD1
K2
VDDS1
K4
ADD2
J5
ADD3
L1 VDD
L2 ADD4
L3
ADD5
M1
ADD6
N1
ADD7
M3 ADD8
M2 ADD9
ADD10
P1
N2
GND
ADD11
TPL16
1
The phone is mainly supplied from the main battery (VBAT) which is
divided into two routes: VBAT is for RF block, vibrator and buzzer;
VBATBB is for baseband block.
The input power (VBATBB) to Nausica is divided into 4 blocks:
VCC1: to provide power for DC/DC and regulator R1 (VR1)
VCC2: to provide power for regulator R1B (VR1B), R2B (VR2B)
and charger pump
VCC3: to provide power for regulator R3 (VR3)
VR2IN: to provide power for regulator R2 (VR2)
NAUSICA provides five low drop-out voltage regulators.
R1 (VR1): 1.8V@50mA; to supply ULYSSE digital core, RTC,
R2 (VR2): 2.9V@120mA; to supply 13MHz clock, external memory
R2B (VR2B): 2.9V@50mA; to supply peripheral devices, I/O to
R1B (VR1B): 2.0V@50mA; to supply the digital part of NAUSICA
R3 (VR3): 2.9V@80mA; to supply analog part of NAUSICA.
BCLKR/ARMCLK
TSPACT10/nWAIT
SIM_PWCTRL/IO5
TSPACT11/MCLK
nRESET_OUT/IO7
CLK13M_OUT/START_BIT
32KHz and the internal SRAM
devices and LCD display
NAUSICA
U1
B13
TSPACT1
A14
VDDS2
C13
TSPACT0
C12
TSPEN3/nSCS2
B14
TSPEN2
C14
TSPDI/IO4
D12
TSPEN1
D13
TSPEN0
D14
TSPDO
F10
VDD
E11
B9
TCXOEN E13
TEST4
A9
EXT_IRQ
E12
TEST3
B8
GND
E14
TEST2
C8
TSPCLKX
F11
TEST1
A8
F12
TMS
B7
BFSR
F13
TCK
A7
BDR
F14
TDI
C7
BFSX
G10
TDO
A6
BCLKX/IO6
G11
TSCYM
B6
VCLKRX G13
TSCXM
C6
BDX
G12
ADIN5/TSCYP
D6
VDDA1
G14
ADIN4/TSCXP
E6
CLKTCXO
H14
ADIN3
A5
GNDA1
H12
ADIN2
B5
VDX H13
ADIN1
C5
VDR
H11
LCDSYNC
D5
VFSRX
H10
SRST5
D4
J14
SIO5
A4
SIM_CLK
J13
CK13M
B4
SIM_IO
J12
SCLK5
C4
J11
SCLK3
A3
SIM_CD/MAS0
K14
VAUX
B3
SIM_RST
K12
SRST3
A2
VDDS2 K13
SVDD
A1
K11
VS2
J10
VDDS1
L14
L13
DATA15 L12
GND M14
DATA14
N14
DATA13
M12
DATA12
M13
DATA11
P14
VDDS1
ULYSSE_uBGA179
BGND
VR1B
BGND
2.0V@50mA
Omega Core
VBATBB
(From Main Battery)
2.9V@50mA
Peripherals
22
Rev 1.0
VR3
2.9V@80mA
Omega/Ulysse Analog part
R22
0
C15 2.2UF
U3
OMEGA
K10
BUZZOP
K9
MICBIAS
J8
MICIN
K8
MICIP
H7
AUXI
J7
AGNDA1
K7
VDR
G7
VFS
G6
VDX
H6
VCK
J6
UDX
K6
UDR
F5
UEN
G5
BFSR
H5
BDR
J5
BFSX
K5
BDX H4
INT2
K4
TEN
J4
TDR
K3
VCC1
H3
COMP
J3
VBACKUP
K2
SWITCH
J2
BGTR5
C21 10UF C17 10UF
C20 10UF R15
BGND
0
C19 2.2UF
BGND
0 0 0
VR2 2.9V@120mA
Memory
VR2B
C26
0.1UF
U4A
2 1
Back-up Battery
C25 0.1UF
VR1
1.8V@120mA
Ulysse Core