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2
Hardware Installation
LPC connector
The Low Pin Count Interface was defined by Intel
dustry's transition towards legacy free systems. It allows the integration of low-
bandwidth legacy I/O components within the system, which are typically provided
by a Super I/O controller. Furthermore, it can be used to interface firmware hubs,
Trusted Platform Module (TPM) devices and embedded controller solutions. Data
transfer on the LPC bus is implemented over a 4 bit serialized data interface, which
uses a 33MHz LPC bus clock. For more information about LPC bus refer to the Intel
Low Pin Count Interface Specification Revision 1.1'.
38
4
1
4
1
5
5
ON
ON
RST#
FRAME#
LAD3
CLK
LAD2
9
1
2
GND
LAD1
VCC3
LAD0
Corporation to facilitate the in-
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