NEC Barracuda Service Manual page 74

4. Pin Descriptions of Major Components
4.1 Intel® StrongARM* SA-1110 Microprocessor-2
Name Type
SDCKE 1:0 OCZ SDRAM and/or SMROM clock enables.
SDCKE 0 should be connected to the clock enable (CKE) pins of
SMROM. SDCKE 0 is asserted upon any rest (including sleep-exit) if
static memory bank 0 (boot space) is configured for synchronous
mask ROM (SMROM_EN = 1); otherwise it is deasserted upon reset.
SDCKE 1 should be connected to the clock enable pins of
SDRAM.They are deasserted (held low) during sleep. SDCKE 1
always is deasserted upon reset. The memory controller provides
control register bits for eassertion of each SDCKE pin. However,
SDCKE 0 cannot be deasserted via program if SMROM_EN =1.
SDCLK 2:0 OCZ SDRAM and/or SMROM clock.
SDCLK 0 should be connected to the clock (CLK) pins of SMROM.
SDCLK 1 and SDCLK 2 should be connected to the clock pins of
SDRAM in bank pairs 0/1 and 2/3, respectively. They are driven by
either the internal memory controller clock (CPU clock divided by 2)
or the memory controller clock divided by 2 (CPU clock divided by
4). All SDCLK pins are held low during sleep mode and start running
at CPU clock divide by 4 upon any reset (including sleep-exit).
The memory controller provides control register bits for clock
division and disable of each SDCLK pin. However, SDCLK 0 cannot
be disabled via program if static memory bank 0 (boot space) is
configured for synchronous mask ROM (SMROM_EN = 1).
RD/nWR OCZ Read/write direction control for memory and PCMCIA data bus (D
31:0). This signal is applicable to all memory bus and PCMCIA
transfers.
For reads (RD/nWR = 1), system-level bus transceivers or directly
connected memory devices should drive D 31:0. For writes (RD/nWR
= 0), the SA-1110 will drive D 31:0.
OCZ PCMCIA output enable. This signal is an output and is used to
nPOE
perform reads from memory and attribute space.
nPWE OCZ PCMCIA write enable. This signal is an output and is used to perform
writes to memory and attribute space.
OCZ PCMCIA I/O write. This signal is an output and is used to perform
nPIOW
write transactions to the PCMCIA I/O space.
nPIOR OCZ PCMCIA I/O read. This signal is an output and is used to perform
read transactions from the PCMCIA I/O space.
nPCE 2:1 OCZ PCMCIA card enable. These signals are output and are used to select
a PCMCIA card. nPCE 2 enables the high-byte lane and nPCE 1
enables the low-byte lane.
IC I/O Select 16. This signal is an input and is an acknowledgment from
nIOIS16
the PCMCIA card that it can perform 16-bit I/O data transfers.
Barracuda PDA Maintenance
Description Name Type
nPWAIT IC PCMCIA wait. This signal is an input and is driven low by the
PCMCIA card to extend the duration of transfers to/from the
SA-1110.
PSKTSEL OCZ PCMCIA socket select. This signal is an output and is used by
external steering logic to route control, address, and data signals to
one of the PCMCIA sockets.
When PSKTSEL is low, socket zero is selected. When PSKTSEL is
high, socket one is selected. This signal has the same timing as the
address lines.
OCZ PCMCIA register select. This signal is an output and indicates that,
nPREG
on a memory transaction, the target address is attribute space. This
signal has the same timing as address.
OCZ LCD controller display data.
L_DD 7:0
L_FCLK OCZ LCD frame clock.
L_LCLK OCZ LCD line clock.
L_PCLK OCZ LCD pixel clock.
L_BIAS OCZ LCD ac bias drive.
OCZ CODEC transmit.
TXD_C
RXD_C IC CODEC receive.
SCLK_C OCZ CODEC clock.
SFRM_C OCZ CODEC frame signal.
UDC+ ICOCZ Serial port zero bidirectional, differential signalling pin (UDC).
ICOCZ Serial port zero bidirectional, differential signalling pin (UDC).
UDC-
TXD_1 OCZ Serial port one transmit pin (UART).
RXD_1 IC Serial port one receive pin (UART).
TXD_2 OCZ Serial port two transmit pin (IrDA).
RXD_2 IC Serial port two receive pin (IrDA).
TXD_3 OCZ Serial port three transmit pin (UART).
RXD_3 IC Serial port three receive pin (UART).
GP 27:0 ICOCZ General-purpose input output.
IC Synchronous mask ROM (SMROM) enable. This pin is used to
SMROM_EN
determine if the boot ROM (static memory bank 0) is asynchronous
or synchronous. If asynchronous, boot ROM is selected
(SMROM_EN = 0) and its width is determined by the state of the
ROM_SEL pin. SMROM is supported only on 32-bit data busses.
Description
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