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1.3.1.1-2 Samsung 128M-bit (8M X 16) Synchronous DRAM
Description:
The K4S281632C is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words
by 16bits, fabricated with SAMSUNG ￠ s high performance CMOS technology. Synchronous design allows
precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory system applications.
Features:
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
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