Supported Gpio Register; Gpio Registers; Gpio Example Program-1 - Advantech PCE-5026 User Manual

Lga1155 intel core i7/i5/i3/pentium picmg 1.3 system host board with ddr3 / sata2.0 / usb2.0 / single gbe lan
Table of Contents

Advertisement

C.1

Supported GPIO Register

Below are the detailed descriptions of the GPIO addresses and programming sam-
ple.
C.2

GPIO Registers

Bank
09h
07h
07h
07h
C.3

GPIO Example Program-1

------------------------------------------------
Enter the extended function mode, interruptible double-write
------------------------------------------------
MOV DX,2EH
MOV AL,87H
OUT DX,AL
OUT DX,AL
--------------------------------------------------------------
-
Configure
CRE0,CRE1,CRE2
--------------------------------------------------------------
-
MOV DX,2EH
MOV AL,09H
OUT DX,AC
DEC DX
MOV AL,30H
OUT DX,AL
INC DX
IN AL,DX
OR AL,10000000B
PCE-5026 User Manual
Offset Description
30h
Write 1 to bit 7 to enable GPIO
GPIO I/O Register
When set to a '1', respective GPIO port is pro-
E0h
grammed as an input port.
When set to a '0', respective GPIO port is pro-
grammed as an output port.
GPIO Data Redister
If a port is programmed to be an output port, then
E1h
its respective bit can be read/written.
If a port is programmed to be an input port, then its
respective bit can only be read.
GPIO Inversion Register
When set to a '1', the incoming/outgoing port value
E2h
is inverted.
When set to a '0', the incoming/outgoing port value
is the same as in data register.
logical
device,
86
configuration
register

Advertisement

Table of Contents
loading

Table of Contents