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In
the
read
mode,
a
potential of +5 volts
D. C.
is applied to the
selected
head
diode
matrix.
The
write mode increases the voltage
applied
LO
the
selected
head
diode matrix to +12 volts D. C. from
the beginning of Write Enable until the end of Internal Write Busy.
write/Erase Circuits
The
write
electronics
consist
of
a
write current source, a write
waveform
generator,
an
erase current source,
the trim erase control
logic, and the side select logic (Figure 4-7).
The
signals required
to control the data electronics provided by the
host controller are:
1.
Drive Select
2.
Wri te Enable
3.
\vrite Data
4.
Side Select
The winding
on
the head is center tapped.
During a write operation,
current from the write current Source flows in alternate halves of the
winding, under control of the write waveform generator.
When
the drive is selected and write protect is false, N Write Enable
initiates the
write
logic.
Seven events that occur are (Figures 4-7
and 4-8):
1.
The pre-erase delay one shot is started, 390 microseconds.
2.
The post-erase delay one shot is started, 900 microseconds.
3.
The post-erase delay one shot outputs a signal:
N Internal
Write Busy.
It is used to disable the Read Data output
circuit, NWRT to increase the read/write diode matrix voltage
from 5 volts D. C. to 12 volts D. C. via the side select
logic during a write operation.
4.
The write current source is enabled via U4.
5.
The write waveform generator has its preset and clear inputs
set to +5 volts D. C. instead of ground (optional).
6.
Input diodes to the read amplifier are reverse biased by
N write to protect the read amplifier during the
write operation.
7.
The write data input is inverted and used to clock the
waveform generator which selects a write driver, thus
providing a ground to forward bias a diode, allowing current
to flow through the coil.
4-9
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