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r - - - - - - - - - + I VOLTS
'nIACK
0, TaT
I"OIMT
10
I
+5 VOLTS
- - - - - - - - - 0 VOLT
_ _ _...J
0 VOLT
I
I
I
Tl\AC:K 0 AD.JUSTHIINT MONITQR POINT
Ie
U8,
PIN
4
TltACKS
ON
-.
-I
--
-3
-2
-1
1liSKITT1!
,TIPPeR
MarcH
0
1
0
1
0
1
PHAAS
o
I
I
I
o
+1
1
+2
o
+ 3 + 4 + 1 + 1
1
a
1
a
FIGURE 4-6
TRACK
0
TIMING
Drive Select
The
Drive
Select
signal is derived from the host controller through
the interface connector.
R39
holds
the
output
of the appropriate select line high until the
line
is
driven
low.
The
signal is buffered through IC U17, which
enables the drive's electronics.
front
panel
L.
E.
D., physically located on the drive motor's,
circuit
board,
is
driven by the select logic through IC U17,
5
and 6, and Ie U7, Pins 11 and
10,
to
provide the NSEL signal
JIO,
pin 5, to the servo circuit board on J4, Pin 5.
This signal
buffered and inverted to activate the front panel L. E. D.
servo
Pins
at
is
The
If
the
drive
is
not selected through the select jumpers and the MX
jumper is not cut, U19, Pins 6 to 11, the drive electronics are active
but the front panel L. E. D. is not on.
4-6
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