Internal I/O Subsystem - IBM Power 595 Technical Overview And Introduction

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When multiple DIMM sizes are ordered, smaller DIMM sizes are placed in the fewest

processor books possible, while insuring that the quantity of remaining larger DIMMs are

adequate to populate at least one feature code per MCM module. The largest DIMM size is

spread out among all remaining processor books. This tends to balance the memory

throughout the system.

For memory upgrades, DIMMs are added first to those books with fewer DIMMs until all books

have the same number of DIMMs. Any remaining memory is then distributed round robin

amongst all books having that size DIMM.

The following memory configuration and placement rules apply to the 595 server:

At initial order, each installed processor book must have a minimum of:

– Four memory units installed (50% populated). The memory units must use the same

DIMM size within the processor book. Different DIMM sizes can be used within the 595

server. For 16 GB DIMMs, memory units must be installed in groups of eight.

– 16 GB of memory activated

Memory upgrades can be added in groups of two units (16 GB DIMMs must be added in

groups of eight units), as follows:

– For memory upgrades, you are not required to add memory to all processor books.

– You must maintain the same DIMM sizes within a processor book when adding

memory.

Processors books are 50% (initial), 75%, or 100% populated. Put another way, each

processor book will have either, four, six, or eight memory units installed.

2.8 Internal I/O subsystem

Each processor book on the 595 server provides four GX busses for the attachment of GX

bus adapters. A fully configured 595 server with eight processor books supports up to 32 GX

bus adapters. The GX bus adapter locations are shown in Figure 2-34.

GX bus adapters (narrow)

GX bus adapters (wide)

Figure 2-34 GX bus adapters

The processor book provides two narrow and two wide GX bus adapter slots. Narrow

adapters fit into both narrow and wide GX bus slots.

IBM Power 595 Technical Overview and Introduction

Node Controllers

Processor Book

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