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2.2 System buses
The POWER6 processor interfaces can be divided into three categories:
SMP interconnect: These interfaces connect the POWER6 processors to each other.
These links form a coherent
network. The links are multiplexed—the same wires are time-sliced among address, data,
and control information.
Local interconnect: Local interfaces communicate the memory structures associated with
a specific POWER6 technology-based chip.
External interconnect: Interfaces provide for communication with I/O devices outside the
central system.
This section discusses the SMP and external interconnects.
2.2.1 System interconnects
The Power 595 uses point-to-point SMP fabric interfaces between processor node books.
Each processor book holds a processor node consisting of four dual-core processors
designated S, T, U and V.
The bus topology is no longer ring-based as in POWER5, but rather a multi-tier,
fully-connected topology in order to reduce latency, increase redundancy, and improve
concurrent maintenance. Reliability is improved with error correcting code (ECC) on the
external I/Os, and ECC and parity on the internal chip wires.
Books are interconnected by a point-to-point connection topology, allowing every book to
communicate with every other book. Data transfer never has to go through another books
read cache to address the requested data or control information. Inter-book communication
takes place at the Level 2 (L2) cache.
The POWER6 fabric bus controller (FBC) is the framework for creating a cache-coherent
multiprocessor system. The FBC provides all of the interfaces, buffering, and sequencing of
address and data operations within the storage subsystem. The FBC is integrated on the
POWER6 processor. The POWER6 processor has five fabric ports that can be used to
connect to other POWER6 processors.
Three for intranode bus interconnections. They are designated as X, Y, and Z and are
used to fully connect the POWER6 processor on a node.
Two for internode bus connections. They are designated as A and B ports and are used to
fully-connect nodes in multi-node systems.
Physically, the fabric bus is an 8-, 4-, or 2-byte wide, split-transaction, multiplexed address.
For Power 595 the bus is 8 bytes and operates at half the processor core frequency
From a fabric perspective, a node (processor book node) is one to four processors fully
connected with XYZ busses. AB busses are used to connect various fabric nodes together.
The one to four processor on a node work together to broadcast address requests to other
nodes in the system. Each node can have up to 8 AB links (two for processor, four processor
per node). Figure 2-13 on page 52 illustrates the internode bus interconnections.
fabric
for system requests in addition to a data routing
Chapter 2. Architectural and technical overview
51
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