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Figure 2-14 POWER5 and POWER6 processor (a) first-level nodal topology and (b) second-level
system topology.
Figure 2-15 on page 55 illustrates the potential for a large, robust, 64-core system that uses
8-byte SMP interconnect links, both L3 data ports to maximize L3 bandwidth, and all eight
memory channels per chip.
54
IBM Power 595 Technical Overview and Introduction
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