IBM Power 595 Technical Overview And Introduction page 64

Figure 2-13 FBC bus connections
The topologies that are illustrated in Figure 2-14 on page 54 are described in Table 2-3.
Table 2-3 Topologies of POWER5 and POWER6
System
(a) POWER5
(a) POWER6
52
IBM Power 595 Technical Overview and Introduction
A B A B
L3 L3 L3 L3 L3 L3 L3
L3 L3 L3 L3 L3 L3 L3
core core core core core core core core core core core core
core core core core core core core core core core core core
L3 L3 L3 L3
L3 L3 L3 L3
Y Y
L3 L3 L3 L3 L3 L3 L3
L3 L3 L3 L3 L3 L3 L3
core core core core core core core core core core core core
core core core core core core core core core core core core
L3 L3 L3 L3
L3 L3 L3 L3
A B A B
Description
The topology of a POWER5 processor-based system consists of a first-level
nodal structure containing up to four POWER5 processors. Coherence links
are fully connected so that each chip is directly connected to all of the other
chips in the node. Data links form clockwise and counterclockwise rings that
connect all of the chips in the node. All of the processor chips within a node
are designed to be packaged in the same multichip module.
The POWER6 processor first-level nodal structure is composed of up to four
POWER6 processors. Relying on the traffic reduction afforded by the
innovations in the coherence protocol to reduce packaging overhead,
coherence and data traffic share the same physical links by using a
time-division-multiplexing (TDM) approach. With this approach, the system
can be configured either with 67% of the link bandwidth allocated for data
and 33% for coherence or with 50% for data and 50% for coherence. Within
a node, the shared links are fully connected such that each chip is directly
connected to all of the other chips in the node.
A B A B
X X
core core core core core core core core core core
core core core core core core core core core core
Z Z
core core core core core core core core core core
core core core core core core core core core core
A B A B
L3 L3 L3 L3 L3 L3 L3 L3
L3 L3 L3 L3 L3 L3 L3 L3
L3 L3 L3 L3
L3 L3 L3 L3
L3 L3 L3 L3 L3 L3 L3 L3
L3 L3 L3 L3 L3 L3 L3 L3
L3 L3 L3 L3
L3 L3 L3 L3