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System
(b) POWER5
(b) POWER6
With both the POWER5 and the POWER6 processor approaches, large systems are
constructed by aggregating multiple nodes.
Description
A POWER5 processor-based system can interconnect up to eight nodes
with a parallel ring topology. With this approach, both coherence and data
links are organized such that each chip within a node is connected to a
corresponding chip in every node by a unidirectional ring. For a system with
four processor s per node, four parallel rings pass through every node. The
POWER5 chip also provides additional data links between nodes in order
to reduce the latency and increase the bandwidth for moving data within a
system.
While the ring-based topology is ideal for facilitating a
nonblocking-broadcast coherence-transport mechanism, it involves every
node in the operation of all the other nodes. This makes it more complicated
to provide isolation capabilities, which are ideal for dynamic maintenance
activities and virtualization.
For POWER6 processor-based systems, the topology was changed to
address dynamic maintenance and virtualization activities. Instead of using
parallel rings, POWER6 process-based systems can connect up to eight
nodes with a fully connected topology, in which each node is directly
connected to every other node. This provides optimized isolation because
any two nodes can interact without involving any other nodes. Also, system
latencies do not increase as a system grows from two to eight nodes, yet
aggregate system bandwidth increases faster than system size.
Of the five 8-byte off-chip SMP interfaces on the POWER6 chip (which
operate at half the processor frequency), the remaining two are dedicated
(A, B - Intranode) to interconnecting the second-level system structure.
Therefore, with a four-processor node, eight such links are available for
direct node-to-node connections. Seven of the eight are used to connect a
given node to the seven other nodes in an eight-node 64-core system. The
five off-chip SMP interfaces on the POWER6 chip protect both coherence
and data with SECDED ECCs.
Chapter 2. Architectural and technical overview
53
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