TMC TI5VGF User Manual page 38

Chapter 6 BIOS Configuration
DRAM Read Pipeline
Sustained 3T Write
Cache Rd+CPU Wt Pipeline
Read Around Write
Cache Timing
Video BIOS Cacheable
System BIOS Cacheable
Memory Hole at 15MB Addr.
AGP Aperture Size
Cyrix M2 ADS# delay
CPU/PCI Clock Select
Auto Detect DIMM/PCI Clk
Spread Spectrum
OnChip USB
USB Keyboard Support
CPU Warning Temperature
Temperature/Fan Speed/Voltage
6.6 Power Management Setup .........................................................47
Power Management
PM Control by APM
Video Off Method
Modem Use IRQ
Soft-Off by PWRBTN
HDD Power Down
Doze Mode
Suspend Mode
PM Events
6.7 PNP/PCI Configuration .............................................................50
PNP OS Installed
Resources Controlled by
Reset Configuration Data
ACPI I/O Device Node
IRQ3/4/5/7/9/10/11/12/14/15, DMA0/1/3/5/6/7 assigned to
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
PCI Master Read Prefetch
PCI#2 Access #1 Retry
AGP Master 1 WS Write
AGP Master 1 WS Read
34 TI5VGF Pentium MVP3 ATX Motherboard User's Manual