Watchdog Timer (Jp2) - Advantech PCI-6771 series User Manual

2.7 Watchdog timer config. (JP2)
An on-board watchdog timer reduces the chance of disruptions which
EMP (electro-magnetic pulse) interference can cause. This is an
invaluable protective device for standalone or unmanned
applications. Setup involves two jumpers and running the control
software. (Refer to Appendix A.)
When the watchdog timer is enabled and the CPU shuts down, the
watchdog timer will automatically either reset the system or
generate an interrupt on IRQ 11, depending on the setting of
jumper JP2, as shown below:
Table 2-4: Watc hdog timer sys tem reset select (JP2)
*System Reset IRQ 11 interrupt
1 1
JP2
* default setting
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