IBM Power7 Optimization And Tuning Manual page 63

The d-cache instructions dcbt (d-cache block touch) and dcbtst (d-cache block touch for
store) affect the behavior of the prefetched lines. The syntax for the assembly language
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instructions is:
dcbt RA, RB, TH
dcbtst RA, RB, TH
RA specifies a source general-purpose register for Effective Address (EA) computation.
RB
specifies a source general-purpose register for EA computation.
TH
indicates when a sequence of d-cache blocks might be needed.
The block that contains the byte addressed by the EA is fetched into the d-cache before the
block is needed by the program. The program can later perform loads and stores from the
block and might not experience the added delay that is caused by fetching the block into
the cache.
The Touch Hint (TH) field is used to provide a hint that the program probably loads or stores
to the storage locations specified by the Effective Address (EA) and the TH field. The hint is
ignored for locations that are caching-inhibited or guarded. The encodings of the TH field
depend on the target architecture that is selected with the -m flag or the .machine assembly
language pseudo-op.
The range of values for the TH field is 0b01000 - 0b01111.
The dcbt and dcbtst instructions provide hints about a sequence of accesses to data
elements, or indicate the expected use. Such a sequence is called a
or dcbtst instruction in which TH is set to one of these values is said to be a
variant
of dcbt or dcbtst.
A data stream to which a program can perform
stream
, and is described using the data stream variants of the dcbt instruction.
A data stream to which a program can perform
stream , and is described using the data stream variants of the dcbtst instruction.
The contents of the DSCR, a special purpose register, affects how the data prefetcher
responds to hardware-detected and software-defined data streams.
The layout of the DSCR register is:
a. POWER7+ only
Where:
Bits 58 – LSD – Load Stream Disable
Disables hardware detection and initiation of load streams.
Bits 59 – SNSE – Stride-N Stream Enable
Enables hardware detection and initiation of load and store streams that have a stride
greater than a single cache block. Such load streams are detected when LSD = 0 and
such store streams are detected when SSE=1.
Bits 60 – SSE – Store Stream Enable
Enables hardware detection and initiation of Store streams.
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Power ISA Version 2.06 Revision B, available at:
http://power.org/wp-content/uploads/2012/07/PowerISA_V2.06B_V2_PUBLIC.pdf
Load
accesses is said to be a
Store
accesses is said to be a
a
URG LSD SNSE
Chapter 2. The POWER7 processor
data stream , and a dcbt
data stream
load data
store data
SSE DPFD
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