IBM Power7 Optimization And Tuning Manual page 40

Additional details about the SMT feature are described in Table 2-1 and Table 2-2.
Table 2-1 Multi-thread per core features by POWER generation
Technology
IBM POWER4
IBM POWER5
IBM POWER6
IBM POWER7
Table 2-2 Multi-thread per core features by single LPAR scaling
Single LPAR scaling
32-core/32-thread
64-core/128-thread
64-core/256-thread
256-core/1024-thread
Operating system enablement usage of multi-core and multi-thread technology varies by
operating system and release.
Power operating systems present an SMP view of the resources of a partition. Hardware
threads are presented as logical CPUs to the application stack. Many applications can use
the operating system scheduler to place workloads onto logical processors and maintain the
SMP programming model. In some cases, the differentiation between hardware threads per
core can be used to improve performance. Placement of a workload on hardware book,
drawer and node, socket, core, and thread boundaries can improve application scaling.
Details about operating system binding facilities are available in 4.1, "AIX and system
libraries" on page 68, and include:
Affinity/topology bindings
Hybrid thread features
Using multi-core and multi-thread features is a challenging prospect. An overview about this
topic and about the application considerations is provided in 4.1, "AIX and system libraries"
on page 68. Additionally, the following specific scaling topics are described in 4.1, "AIX and
system libraries" on page 68:
pthread tuning
malloc tuning
For more information about this topic, see 2.4, "Related publications" on page 51.
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POWER7 and POWER7+ Optimization and Tuning Guide
Cores/system Maximum SMT
mode
32 ST
64 SMT2
64 SMT2
256 SMT4
AIX release
5.3/6.1/7.1
5.3/6.1/7.1
6.1(TL4)/7.1
7.1
Maximum hardware
threads per LPAR
32
128
128
1024
Linux
RHEL 5/6
SLES 10/11
RHEL 5/6
SLES 10/11
RHEL 6
SLES 11sp1
RHEL 6
SLES 11sp1