Analog Signal Processing Domain; Digital Signal Processing Domain - Sony BVP-900 Series Product Information Manual

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SONY ADVANCED DIGITAL SIGNAL PROCESSING (ADSP)
Spatial Offset Technology to provide higher resolution. The image
captured on the photosensors of each CCD is read out at a clock
frequency of 18 MHz.

4-3. Analog Signal Processing Domain

Gain boost process is performed in the analog domain by a Video
Amplifier circuit. After that white balance and pre-knee are processed
with an AD board. The video signal from the CCD, which can have a
dynamic range of 600% of nominal white level, is compressed to
approximately 340% by this pre-knee process and converted to a 12-
bit digital signal at an 18 MHz sampling rate. This is the same
sampling frequency as that of the Power HAD 1000 imager.

4-4. Digital Signal Processing Domain

The camera signal processing is executed in the digital domain in
BVP-900 Series cameras. Within this digital processing, more than 12
bits are used in critical applications such as shading compensation,
image enhancing and gamma correction.
As shown in the diagram, three VLSIs are used for processing. In the
SH VLSI, the peak and average levels are measured, together with
other parameter of the video signal. These measurements are sent to
the analog circuits as feedback signals. The PR circuit contains the
main camera processing; gamma controls, knee slope controls and so
on. The RC circuit is used for aspect ratio conversion between 16:9
and 4:3. The ARC is a separate board supplied with widescreen,
switchable, OHB CCDs. The SH, IE, PR and ARC are using the latest
VLSI technologies.
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