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PREPARATION FOR USE
Table 2-18.
Multibus· Interface Arbitration Options
Interface
Jumper
State
Connect
State
State
Description
1
2
E213-E214
E202-E201
LOW
LOW
HIGH LOW
E213-E214
E202-E203
LOW
HIGH
The Bus Arbiter that has control of the
Multibus interface retains control
unless a higher priority master
deactivates BPRN/ or unless the next
machine cycle does not require the use
of the Multibus interface.
It may then
relinquished to a lower priority device.
The Bus Arbiter that has control of the
Multibus interface retains control until
another Bus Arbiter pulls CBRQ/ low.
When CBRQ/ goes low, the conditions are
as described above.
The Bus Arbiter that controls the
Multibus interface surrenders control to
the Bus Arbiter that is pulling CBRQ/
low, regardless of its priority, upon
completion of the current bus cycle.
HIGH
HIGH
The Bus Arbiter controlling the Multibus
interface retains control until another
Bus Arbiter pulls CBRQ/ low.
When CBRQ/
goes low, the conditions are as
described above.
3
E212-E213
2-29.
E202-E203
LOW
HIGH
The Bus Arbiter controlling the Multibus
interface surrenders the use of the
Multibus interface after each transfer
cycle.
MULTIBUS INTERFACE SPECIFICATIONS
For systems applications, the iSBC 86/14/30 board is designed for
installation in a standard Intel iSBC System Modular Backplane and
Cardcage.
The iSBC 86/14/30 board can interface to a user-designed
system backplane by means of an 86-pin connector.
Multibus interface
signal characteristics and methods of implementing a serial or parallel
priority resolution scheme for resolving bus contention in a multiple bus
master system are described in the following paragraphs.
.
2-50
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