Pci Asynchronous Mode Instruction Word Format; Pci Asynchronous Mode Transmission Format - Intel iSBC 86/14 Hardware Reference Manual

PROGRAMMING INFORMATION
I S , l
s,
I EP IpENILl IL' I B, I B, I
L
BAUO RAT[ FACTOH
0 1 0 1
0 0
1 1
SYNC
(1 X ~ (16Xt (64XI
MODE
CHARACTER LENGTH
0
1 0 1
0
0 1 1
;
6 7 B
BITS BITS BITS BITS
PARITY ENABLE
1 ENABLE 0 DISABLE
EVEN PARITY GENERAT10N'CHE
1
EVEN 0
ODD
NUMBER OF STOP BITS
0 1 0 1
0
0 1 1
INVALID
1 1", 2
BIT
BITS BITS
(ONLY EFFECTS TX; RX NEVER
REOUIRES MORE THAN ONE
STOP BIT)
CK
Figure 3-6.
PCI Asynchronous Mode Instruction Word Format
GENERATED
TRANSMITTER OUTPUT
Ox BY 8251A
TXD
S T J ; i
BITS
L
RECEIVER INPUT
DOD, - - -Oil.
DOES NOT APPEAR
ON THE DATA BUS
RXD
START
BIT
1
t
1---'-1
-r--:""'--r---I
DATA:BITS
ST~
" BITS
L
- -
PROGRAMMED
CHARACTER
LENGTH
TRANSMISSION FORMAT
CPU BYTE 158 BITS/CHAR I
DATA
C~~RACTER
ASSEMBLED SERIAL DATA OUTPUT (Txm
ClATA CHARACTER
BITS
STOD
~------~----~--~
RECEIVE FORMAT
SERIAL DATA INPUT IR,DI
DATA CHARACTER
SlOO
L -____
~~
________
~~
______
~
______
~
___
B~'TS
Figure 3-7.
CPU BYTE 15 B BITS/CHARI"
"NDTE IF CHARACTER LENGTH IS DEFINED AS 5 6 OR 7
BITS THE UNUSED BITS ARE SET TO "lER'O"
PCI Asynchronous Mode Transmission Format
3-20