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PREPARATION FOR USE
2-42.
POWER FAIL BATTERY BACKUP PROVISIONS
In an optional mode, the iSBC 86/14/30 board may be configured for
battery backup operation.
This means you may connect a dc battery to the
board to perserve mamory during an ac power failure.
In order for the
battery backup scheme to function, your power supply must provide the
following signals:
a.
PFIN/
b.
MPRO/
c.
PFSN/
Power Fail Interrupt.
Asserted at least 8 milliseconds
before dc voltages are lost.
Memory Protect.
Asserted at least 50 microseconds before
dc voltages are lost.
Power Fail Sense.
The output of an external, battery
powered latch which indicates a power failure has
occurred.
To implement a typical battery backup scheme on the iSBC 86/14/30 board,
the following connections are required:
a.
Connect +5 Volt battery positive leads to auxiliary connector
pins P2-3 and P2-4.
b.
Connect battery return leads to auxiliary connector pins P2-1,
P2-2, and P2-22.
c.
Remove jumper connections El14-El15 and E277-E278.
d.
Connect the power supply PFIN/ line to auxiliary connector P2-19.
e.
Remove interrupt jumper E144-E145 and install jumper E145-E168.
This routes the PFIN/ input to the NMI input on the 8086-2 CPU.
f.
Ensure that the NMI signal is not masked by programming a 1 into
the Status Register, bit 2.
g.
Connect the power supply MPRO/ line to auxiliary connector P2-20.
h.
Connect the PFSN/ line to auxiliary connector P2-17.
PFSN/ is
the output of an external, battery powered latch which indicates
that a power failure has occurred.
In this typical battery backup configuration, if a power failure occurs,
the power supply asserts PFIN/, which in turn initiates the NMI
interrupt.
The interrupt request causes the 8086-2 CPU to store the
contents of the various internal registers into RAM, and the interrupt
software stores any other information that must be saved.
When the MPRO/
signal is asserted, all accesses to the RAM are disabled.
When the power
is restored, the PFSN/ signal indicates that a power failure has
occurred.
Your power-on routine could then read the contents of RAM
before executing, thereby minimizing data loss.
2-76
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