Lambda Genesys GENH 750W Technical Manual page 73

The SRQ message is: "Inn" terminated by CR, where the nn is the power supply address. The
SRQ will be generated either in Local or Remote mode.
Refer to Tables 7-10 to 7-13 for details of the Enable and Event registers.
1. Fault Enable Register
The Fault Enable Register is set to the enable faults SRQs.
Table 7-10: Fault Enable Register
Enable
BIT
bit name
0 (LSB) Spare bit
1 AC Fail
2 Over Temperature
3 Foldback
4 Over Voltage
5 Shut Off
6 Output Off
7(MSB) Enable
2. Fault Event Register
The Fault Event will set a bit if a condition occurs and it is Enabled. The register is cleared when
FEVE?, CLS or RST commands are received.
Table 7-11: Fault Event Register
Enable
BIT
bit name
0 (LSB) Spare bit
1 AC Fail
2 Over Temperature
3 Foldback
4 Over Voltage
5 Shut Off
6 Output Off
7(MSB) Enable
Fault symbol Bit Set condition
SPARE
AC
User command:
OTP
"FENA nn" where
FOLD
nn is hexadecimal
OVP
SO
OFF
ENA
Fault symbol Bit Set condition
SPARE
AC
Fault condition
occurs and it is
OTP
enabled.
FOLD
The fault can set a
bit, but when the
OVP
fault clears the bit
remains set.
SO
OFF
ENA
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Bit reset condition
User command: "FENA nn"
where nn is hexadecimal (if
nn="00", no fault SRQs will
be generated).
Bit reset condition
Entire Event Register is
cleared when user sends
"FEVE?" command to read
the register.
"CLS" and power-up also
clear the Fault Event Reg-
ister. (The Fault Event
Register is not cleared by
RST)