Appendix 1 - J&W G31 + ICH7 Chipset User Manual

G31 Series

APPENDIX 1

POST Codes
NOTE: EISA POST codes are typically output to port address 300h.
ISA POST codes are output to port address 80h.
Code
(hex) Name
C0 Turn Off Chipset Cache
1 Processor Test 1
2 Processor Test 2
3 Initialize Chips
4 Test Memory Refresh
Toggle
5 Blank video, Initialize
keyboard
6 Reserved
7 Test CMOS Interface and Verifies CMOS is working correctly, detects bad battery.
Battery Status
BE Chipset Default
Initialization
C1 Memory presence test
C5 Early Shadow
C6 Cache presence test
8 Setup low memory
Description
OEM Specific-Cache control
Processor Status (1FLAGS) Verification. Tests the following
processor status flags: carry, zero, sign, overflow, The BIOS
sets each flag, verifies they are set, then turns each flag off
and verifies it is off.
Read/Write/Verify all CPU registers except SS, SP, and BP with
data pattern FF and 00.
Disable NMI, PIE, AIE, UEI, SQWV Disable video, parity
checking, DMA Reset math coprocessor. Clear all page
registers, CMOS shutdown byte. Initialize timer 0, 1, and 2,
including set EISA timer to a known state. Initialize DMA
controllers 0 and 1. Initialize interrupt controllers 0 and 1.
Initialize EISA extended registers.
RAM must be periodically refreshed to keep the memory from
decaying. This function ensures that the memory refresh
function is working properly.
Keyboard controller initialization.
Program chipset registers with power on BIOS defaults.
OEM Specific-Test to size on-board memory.
OEM Specific-Early Shadow enable for fast boot.
External cache size detection.
Early chip set initialization. Memory presence test OEM chip
set routines. Clear low 64K of memory. Test first 64K memory.
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User's Manual