Appendix 1 - J&W nVIDIA MCP78 Series User Manual

nVIDIA MCP78 Series

APPENDIX 1

AMIBIOS Check Point and Code List:
1.Bootblock Initialization Code Checkpoints
The Bootblock initialization code sets up the chipset, memory and other
components before system memory is available. The following table describes the
type of checkpoints that may occur during the bootblock initialization portion of
the BIOS:
Checkpoint Description
Early chipset initialization is done. Early super I/O
Before D1 initialization is done including RTC and keyboard controller.
NMI is disabled.
Perform keyboard controller BAT test. Check if waking up
D1 from power management suspend state. Save power-on
CPUID value in scratch CMOS.
Go to flat mode with 4GB limit and GA20 enabled. Verify the
D0
bootblock checksum.
Disable CACHE before memory detection. Execute full
D2
memory sizing module. Verify that flat mode is enabled.
If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock
D3
code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled.
D4 Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now
D5
executes out of RAM.
Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced.
D6 Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0. See
Bootblock Recovery Code Checkpoints section of document for more information.
Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to
D7
system memory and control is given to it. Determine whether to execute serial flash.
D8 The Runtime module is uncompressed into memory. CPUID information is stored in memory.
Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves
D9
all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM.
Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See
DA
POST Code Checkpoints section of document for more information.
2.Bootblock Recovery Code Checkpoints
The Bootblock recovery code gets control when the BIOS determines that a
BIOS recovery needs to occur because the user has forced the update or the
BIOS checksum is corrupt. The following table describes the type of checkpoints
that may occur during the Bootblock recovery portion of the BIOS:
Checkpoint Description
Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA
E0
controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9 Set up floppy controller and data. Attempt to read from floppy.
EA Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB Disable ATAPI hardware. Jump back to checkpoint E9.
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User's Manual