SOLTEK SL-65KIV User Manual page 65

CPU to PCI Write
Buffer
PCI Dynamic Bursting When Enabled, every write transaction goes to the
PCI Master 0 WS Write When Enabled, writes to the PCI bus are executed
PCI Delay Transaction Leave this field at default.
PCI # 2 Access # 1
Retry
AGP Master 1 WS
Write
AGP Master 1 WS
Read
Memory Parity/ECC
Check
3. Press <ESC> to return to the Main Menu when you finish setting up all
items.
When this field is Enabled, writes from the CPU to
the PCI bus are buffered, to compensate for the
speed differences between the CPU and the PCI
bus. When Disabled, the writes are not buffered and
the CPU must wait until the write is complete before
starting another write cycle.
The choices: Enabled; Disabled.
write buffer. Bursting transactions then burst on the
PCI bus and non-bursting transactions don't.
The choices: Enabled; Disabled.
with zero wait states.
The choices: Enabled; Disabled.
The choices: Enabled; Disabled(default).
Leave this field at default.
Leave this field at default.
This item enabled to detect the memory parity and
Error Checking & Correcting.
The choices: Enabled; Disabled.
65
BIOS Setup