SOLTEK SL-65KIV User Manual page 63

DRAM Timing By SPD When this item Enabled, DRAM Timing is set by
DRAM Clock The value represents the performance parameters
SDRAM Cycle Length Select CAS latency time in HCLKs of 2 or 3. The
Bank Interleave The choices: Disabled; 2 Bank; 4 Bank.
Memory Hole In order to improve performance, certain space in
P2C/C2P Concurrency This item allows you to enable/disable the PCI to
System BIOS
Cacheable
Video RAM Cacheable Selecting Enabled allows caching of the video memory
SPD.
SPD (Serial Presence Detect) is located on the
memory modules, BIOS reads information coded in
SPD during system boot up.
of the installed memory chips (DRAM). Do not
change the value from the factory setting unless you
install new memory that has a different performance
rating.
system designer already set the values. Do not
change the default value unless you change speci-
fications of the installed DRAM or the installed CPU.
memory is reserved for ISA cards. This memory must
be mapped into the memory space below 16MB.
The choices: 15M-16M; Disabled.
CPU, CPU to PCI concurrency.
The choices: Enabled; Disabled.
Selecting Enabled allows caching of the system
BIOS ROM at F0000h-FFFFFh, resulting in better
system performance.
(RAM) at A0000h-AFFFFh, resulting in better video
performance. However, check your AGP manual to
find out if any compatibility problem exists.
63
BIOS Setup