Pci Controller - Dalsa PC2-CamLink User Manual

IFC

PCI Controller

PCI controller has scatter-gather support to reduce CPU usage to a minimum. It retrieves a buffer
descriptor list from host memory. The PCI controller can sustain an average transfer rate up to
100MB/second with bursts of 132MB/second. Note that the PC2-CamLink provides a 4KB data FIFO
between the acquisition circuitry and the PCI controller. It does not have any onboard frame buffers.
Note: Achievable sustained transfer rates depend on how many PCI devices are trying to utilize bus
master on the PCI bus concurrently. For optimal performance while grabbing, ensure that the PC2-
CamLink is the only device utilizing the bus master on the PCI bus. Otherwise, if sufficient PCI
bandwidth is unavailable, a discarded frame can result.
PCI Bandwidth Discussion
Bandwidth is usually expressed in MB per seconds (MBps). The classic 32-bit PCI bus has a 32-bit
wide data bus, with a clock rate of 33.3MHz. The maximum theoretical transfer speed is 4bytes (32-
bit) * 33.3MHz = 133MB per second. However, since the PCI bus communication protocol introduces
overhead and that other devices are accessing the PCI bus, the practical capacity is generally around
60-80MB per second and is highly dependant upon your PCI chipset. In general:
1. If the required bandwidth is smaller than 60MB per second, it should be acceptable for most
PC systems available on the marketplace today.
2. If the required bandwidth has a range between 60MB per second to 80MB per second,
precaution must be considered towards the system's chipset quality and towards other PCI
devices installed within the same system.
3. Bandwidth larger than 80MB per second cannot reliably be handled by PC2-CamLink
because of its FIFO-based architecture. Consider using the DALSA PC-CamLink or X64-CL
in this case. These latter boards provide enough onboard memory to compensate for PCI
latencies.
Because the PC2-CamLink transfer engine is using a 4KB FIFO for transfers, when the PC2-CamLink
is acquiring and transferring an image simultaneously, the FIFO gets filled at the maximum speed
during one line period. If the line size is smaller than 4KB, the line blanking period will allow the
FIFO to be emptied. However, a line size larger than 4KB requires the availability of the PCI bus
when the frame grabber transfers an image. This leads to two different methods of bandwidth
computation required by a particular camera.
Note: The line bandwidth is the limiting factor for both area scan and linescan cameras since the
onboard FIFO is not large enough to store a whole image. Even for area scan cameras, you must
ensure that the line bandwidth being output by the camera fits within the PCI bus range.
PC2-CamLink User's Manual
IFC Support for YCrCb Engine:
Create an image connection using IfxCreateImgConn() with the flag
IFC_YCRCB_SINK or use IfxCreateImgSink() with the YCRCB_SINK flag.
Part I: PC2-CamLink Board • 49