Table 1-1 Mvme3100 Features Summary - Emerson MVME3100 Series Programmer's Reference Manual

Board Description and Memory Maps
Figure 1-1 shows a block diagram of the MVME3100 and
MVME3100.
Figure 1-1 Block Diagram
GigE COM1
RJ45 RJ45
XCVR
RS232
PHY
5461
PHY
5461
PHY
5221
GigE 2

Table 1-1 MVME3100 Features Summary

Feature
Processor/Host
Controller/Memory Controller
16
RST/ABORT
U
S PMC 1 Front IO
sATA
B
Serial Port 0
DUART
GigE 1
TSEC1
GigE 2
TSEC2
10/100
FEC
Serial Ports 1-4
De-pop in -1152
P2P
PCI6520
PMCSpan
Bus C
PCI 33 MHz
USB
uPD720101
USB 1 USB 2
XCVR
RS232
10/100 COM2 - COM5 PMC 1 Jn4 IO
P2
Description
– Single 667/833 MHz MPC8540 PowerQUICC III™ integrated
processor (e500 core)
– Integrated 256KB L2 cache/SRAM
– Integrated four-channel DMA controller
– Integrated PCI/PCI-X controller
– Two integrated 10/100/1000 Ethernet controllers
– Integrated 10/100 Ethernet controller
– Integrated dual UART
– Integrated I2C controller
– Integrated programmable interrupt controller
– Integrated local bus controller
– Integrated DDR SDRAM controller
MVME3100 Single Board Computer Programmer's Reference (6806800G37A)
Table 1-1
Front Panel
166 MHz Memory Bus
SODIMM - Up to
1GB DDR Memory
DDR MC
I 2 C Bus
MPC8540
I2C
Processor
Device
833 MHz
Bus
LBC
PCIX
Quart
16C554
Bus A
PCI-X 66MHz
P2P
PCI6520
Bus B
PCI-X 66/100 MHz
PCI 33/66 MHz
sATA
PMC 1 PMC 2
GD31244
sATA 0
VME Bus
I 2 C Bus
USB 2
Future Option
lists the features of the
PMC 2 Front IO
User RTC VPD
128KB DS1375 8KB
CPLD
RTC
Decode
Timers/Regs
DS1621
Flash
128MB
Clock
Distribution
Reset
Control
Power
Supplies
VME
TSI148
sATA 1
Planar XCVR
Connector 22501
sATA 2
P0 P1
Overview