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Board Description and Memory Maps
Table 1-18 Test Register 2 (continued)
REG
OPER
RESET
TEST2: A read from this address returns the complement of the data pattern in test register 1.
A write to this address writes the uncomplemented data to register TEST1.
1.3.16
External Timer Registers
The MVME3100 provides a set of tick timer registers for access to the four external timers
implemented in the timers/registers PLD. These registers are 32-bit registers and are not byte
writable. The following sections describe the external timer prescaler and control registers.
1.3.16.1 Prescalar Register
The prescaler provides the clock required by each of the four timers. The tick timers require a
1 MHz clock input. The input clock to the prescaler is 25 MHz. The default value is set for $E7,
which gives a 1 MHz reference clock for a 25 MHz input clock source.
Table 1-19 Prescalar Register
REG
BIT
FIELD
OPER
RESET
Prescalar Adjust: The prescaler adjust value is determined by the following formula:
Prescaler adjust = 256 - (CLKIN/CLKOUT) where CLKIN is the input clock source in MHz and
CLKOUT is the desired output clock reference in MHz.
1.3.16.2 Control Registers
The prescaler provides the clock required by each of the four timers. The tick timers require a
1 MHz clock input. The input clock to the prescaler is 25 MHz. The default value is set for $E7,
which gives a 1 MHz reference clock for a 25 MHz input clock source.
Table 1-20 Tick Timer Control Registers
REG
BIT
30
Test Register 2 - 0xE2000014
R/W
FFFF
Prescalar Register - 0xE2020000 (8 bits of 32)
7
6
5
Prescalar Adjust
R/W
$E7
Tick Timer 1 Control Register - 0xE2020010 (32 bits)
Tick Timer 2 Control Register - 0xE2020020 (32 bits)
Tick Timer 3 Control Register - 0xE2020030 (32 bits)
Tick Timer 4 Control Register - 0xE2020040 (32 bits)
31
...
11
10
9
MVME3100 Single Board Computer Programmer's Reference (6806800G37A)
4
3
2
8
7
6
5
4
External Timer Registers
1
0
3
2
1
0
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