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External Timer Registers
Table 1-20 Tick Timer Control Registers (continued)
REG
FIELD
OPER
RESET
ENC: Enable counter. When this bit is high, the counter increments. When this bit is low, the
counter does not increment.
COC: Clear counter on compare. When this bit is high, the counter is reset to 0 when it
compares with the compare register. When this bit is low, the counter is not reset.
COVF: Clear overflow bits. The overflow counter is cleared when a 1 is written to this bit.
OVF: Overflow bits. These bits are the output of the overflow counter. The overflow counter is
incremented each time the tick timer sends an interrupt to the local bus interrupter. The overflow
counter can be cleared by writing a 1 to the COVF bit.
ENINT: Enable interrupt. When this bit is high, the interrupt is enabled. When this bit is low, the
interrupt is not enabled.
CINT: Clear interrupt.
INTS: Interrupt status.
RSVD: Reserved for future implementation.
1.3.16.3 Compare Registers
The tick timer counter is compared to the Compare register. When they are equal, the tick timer
interrupt is asserted and the overflow counter is incremented. If the clear-on-compare mode is
enabled, the counter is also cleared. For periodic interrupts, this equation should be used to
calculate the compare register value for a specific period (T):
Compare register value = T (us)
MVME3100 Single Board Computer Programmer's Reference (6806800G37A)
Tick Timer 1 Control Register - 0xE2020010 (32 bits)
Tick Timer 2 Control Register - 0xE2020020 (32 bits)
Tick Timer 3 Control Register - 0xE2020030 (32 bits)
Tick Timer 4 Control Register - 0xE2020040 (32 bits)
R/W
0
...
0
0
0
Board Description and Memory Maps
0
0
0
0
0
0
0
0
0
31
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