Vme Memory Map; System I/O Memory Map; Table 1-5 System I/O Memory Map - Emerson MVME3100 Series Programmer's Reference Manual

Board Description and Memory Maps
Table 1-4 MOTLoad's Processor Address Map (continued)
Processor Address
Start
bottom_flash
1. Reserved for future larger flash devices.
2. The flash is ligically one back but may be physically implemented in two banks.
After RESET, the MPC8540 does not map any PCI memory space (inbound or outbound), and
does not respond to Config cycles.
1.3.3

VME Memory Map

The MVME3100 is fully capable of supporting both the PReP and the CHRP VME Memory Map
examples with RAM size limited to 2GB.
1.3.4

System I/O Memory Map

System resources including System Control and Status registers, external timers, and the
QUART are mapped into a 16MB address range from the MVME3100 via the MPC8540 local
bus controller (LBC). The memory map is defined in the following table, including the LBC bank
chip select used to decode the register:

Table 1-5 System I/O Memory Map

Address
E200 0000
E200 0001
E200 0002
E200 0003
E200 0004
E200 0005
E200 0006
E200 0007
E200 0008
E200 0009
E200 000C
E200 0010
E200 0014
E200 0018 -
E200 0FFF
20
End Size
FFFF FFFF flash_size
(128MB max)
Definition
System Status Register
System Control Register
Status Indicator Register
Flash Control/Status Register
PCI Bus A Status Register
PCI Bus B Status Register
PCI Bus C Status Register
Interrupt Detect Register
Presence Detect Register
PLD Revision
PLD Date Code (32 bits)
Test Register 1 (32 bits)
Test Register 2 (32 bits)
Reserved
MVME3100 Single Board Computer Programmer's Reference (6806800G37A)
Definition
Flash
LBC Bank /
Chip Select
2
2
2
2
2
2
2
2
2
2
2
2
2
VME Memory Map
Notes
2
Notes
3
3
3
3
3
3
3
3
3
3
3
3
3
1