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11.1 Instructions for control of the ADC-Module
11.1.1 Register Addresses 0 – 3: EEPROM control
The EEPROM control is identical to the sensor module case. Appendix D describes the
access of the EEPROM via the RS232 interface. The register assignments of the ADC
module are shown in detail in Appendix B.
11.1.2 Register Address 4: Status information of the ADC-Module
The ADC module status is shown in status register 3 (see Table 23). Bit 2 is set to "1"
and labels the ADC module. Bits 0 and 1 of status register 3 contain information about
the state of the EEPROM when storing camera settings. If the camera is in the
AUTOLOAD state (after power-on or reset of the camera), the settings are being copied
from the EEPROM to the internal registers. During this phase, EEPROM access is not
permitted because otherwise incorrect information will get into the internal
camera register. The PROM_BUSY state indicates an uncompleted writing cycle (active
memory load) during write access to the EEPROM. EEPROM access in this condition
should always be avoided!
Table 23: Status register 3 (register address REGADDR = 4D = 04H)
STATUS3_REG
bit
Description
0
AUTOLOAD, signalizes active Power-Up or Reload of data from EEPROM,
write access forbidden
1
PROM_BUSY, write access forbidden
2
= 1, bit always high, coding for ADC module
3
Not used, arbitrary logical state
4
Not used, arbitrary logical state
5
Not used, arbitrary logical state
6
Not used, arbitrary logical state
7
Not used, arbitrary logical state
11.1.3 Register Address 6: Basic modes and ADC-condition
Bit 0 of the mode register must be set to 1 to access and modify the RAM-LUT via the
registers 08H – 0AH. With bit 1 selects the USER-LUT0 or USER-LUT1, during the reload
phase. To select the USER-LUT1 into the RAM-LUT, bit 1 must be set and followed by a
reload of the LUT.
REV: 1.0
MV-D752-28 User's Manual
Page 36/61
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