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Table 27 (continuation): EEPROM Functions and Assignment to internal FPGA
register
Name
Description
BANK0_BYTE0[7:0]
Global Offset Low Gain LSB
BANK0_BYTE1[7:0]
Global Offset Low Gain MSB
BANK0_BYTE2[7:0]
Global Offset High Gain LSB
BANK0_BYTE3[7:0]
Global Offset High Gain MSB
BANK0_BYTE4[7:0]
No LinLog LSB (LL2)
BANK0_BYTE5[7:0]
No LinLog MSB (LL2)
BANK0_BYTE6[7:0]
Log Parameter LSB
BANK0_BYTE7[7:0]
Log Parameter MSB
BANK0_BYTE8[7:0]
LinLog Parameter LSB (LL1)
BANK0_BYTE9[7:0]
LinLog Parameter MSB (LL1)
BANK0_BYTE10[7:0]
No Skimming LSB
BANK0_BYTE11[7:0]
No Skimming MSB
BANK0_BYTE12[7:0]
Skimming 0 LSB (1.40V factory setting)
BANK0_BYTE13[7:0]
Skimming 0 MSB
BANK0_BYTE14[7:0]
Skimming 1 LSB (1.18V factory setting)
BANK0_BYTE15[7:0]
Skimming 1 MSB
Abbreviations:
R:
Read
W:
Write
C:
Command
DEC:
Decimal value
HEX:
Hexadecimal value
*
(
):
bit 2 to bit 7 arbitrary value
(**)
:
adjusted value
REV: 1.0
MV-D752-28 User's Manual
R/
PROM
FPGA
W
Address
Register
or C
Address
HEX
HEX
R/W
5D
30
R/W
5E
31
R/W
5F
32
R/W
60
33
R/W
61
34
R/W
62
35
R/W
63
36
R/W
64
37
R/W
65
38
R/W
66
39
R/W
67
3A
R/W
68
3B
R/W
69
3C
R/W
6A
3D
R/W
6B
3E
R/W
6C
3F
Default
HEX
(**)
94
(**)
36
(**)
83
37
(**)
(**)
00
(**)
30
(**)
F4
(**)
31
(**)
BC
(**)
32
FF
(**)
(**)
2F
(**)
58
(**)
2E
(**)
F4
2D
(**)
Page 42/61
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