Onkyo TX-SA806 Service Manual page 98

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -41
Q8200: FLI30336 (Video Processor, TORINO)
BLOCK DIAGRAM
DIP_PIP_CLK
DIP
IPCLK0
IPCLK1
CLK
DIP_MAIN_CLK
IPCLK2
MUX
IPCLK3
DIG_PORTA[23:0]
AODD
HS
AHSYNC
AVSYNC
VS
DIP_CSYNC
AHS_CS_RAW
AEXT_CLAMP
AEXT_COAST
DIG_PORTB[23:0]
BODD
BHSYNC
BVSYNC
V1_
ADC A
V1_
ADC B
V1_
ADC C
A1
A2
A3
V1_Sync
A4
ADC
A_RETUR
B1
B2
V1_Sync
B3
Slicer
B4
B_RETUR
C1
C2
C3
C4
C_RETUR
SV1
SV2
V2_
SV3
ADC A
SV4
SV_RETUR
VOUT V2_
ADC B
V2_
ADC C
V2_Sync
ADC
V2_Sync
Slicer
Clock Gen
SDDS2
EDDS2
SDDS
EDDS
ODDS
FDDS
Bootstrap DDDS
RCLK
TCLK
RCLK
OSC
PLL
19.6608MHz
Digital Input Port(DIP)
656
Decoder
PIP
PIP
Port Bus Bus
Select Swap
Flip
656
MAIN MAIN
Decoder
Bus
Bus
Swap Flip
V1_Decimation
Filter
Input
V1_Decimation
Select
Filter
3D Video Mux
Decoder
V1_Decimation
Filter
Sync
Processor
VBI Slicer
SCART
Overlay
V2_Decimation
Filter
V2_Decimation
Filter
V2_Decimation
Filter
Sync
Processor
On Chip Microcontroller(OCM)
Update
Controller
SCLK2
IRQ Controller
ECLK2
Reset
Controller
DWORD Co-processor
SCLK
ECLK
OCLK
Host
FCLK Register
DCLK Interface
PWM GPIO IR
TCLK
JTAG Boundary
Scan
iAVS_CLK
PIP Channel
Input PIP Processor(IPP)
IWC
TPG
Neas PXL
RGB2YUV
Win Grab
4:4:4-4:2:2
Sum
Feat LTR
IBD WSS
MAIN
Diff Det Box
IFM
IFM3
to MC
MAIN Channel
PIP
IFM
Input Main Processor(IMP)
IVP
3:2
TPG
Pull
TNR+
CCS
Down
+
PXL RGB2YUV
Neas
Win Grab
4:4:4-4:2:2
Sum
Feat
IBD WSS
Diff Det
Dynamic Scaler
Controller
FS Bridge
Turbo186
Table Access
Code Bridge
JTAG Patch
64K ROM
x186 Bus
64K SRAM
I2C
Ext
JTAG I2C
I2C Low Band Width
RAM/ROM Slave
Bridge
ddc2bi Master
ADC
I/F ddc2bi
PIP Vertical Filter(PVF) PIP Horizontal Filter(PHF)
Horizontal
DCDi
Scaler
Vertical Scaler
Peaking Filter
Peaking Filter
PIP Channel Data Router
from MC
Main Vertical Filter(MVF) Main Horizontal Filter(PHF)
DCDi
Horizontal
MADi
MPEG Scaler
Vertical Scaler
Noise
Reduction
Peaking Filter
Peaking Filter
Main Channel Data Router
Memory Controller(MC)
OSD CTRL
HW Engine
Arbiter
Address Generator
FRC Controller
I2S
DDR Memory Interface Controller
TX-SR806/SA806
Output Display
Processor
Edge
Enhancement
4:2:2-4:4:4
4:2:2-4:4:4
RGB2YUV
ACC+
ACM-3D
(Blue Stretch)
3x3 Matrix
3x3 Matrix
Multipip
PIP/MAIN
Engine
Blender
Video LUT
Gamma
Dither
Response Time Enhancement
OSD
Blender
Display Engine
LVDS
Interface
LVDS
Mapping
PXL
TTL
Grab
Interface
Display
Panel
Timing Master
Power
Generator Slave Sync
CTRL