Onkyo TX-SA806 Service Manual page 92

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-35
Q8501 : SII9135ACTU ( HDMI Receiver)
TERMINAL DESCRIPTION(1/3)
Digital Video Output Pins
Pin Name Pin # Dir
Q0 16 Output
Q1 15 Output
Q2 14 Output
Q3 13 Output
Q4 10 Output
Q5 9 Output
Q6 8 Output
Q7 7 Output
Q8 3 Output
Q9 2 Output
Q10 1 Output
Q11 144 Output
Q12 141 Output
Q13 140 Output
Q14 139 Output
Q15 138 Output
Q16 135 Output
Q17 134 Output
Q18 133 Output
Q19 132 Output
Q20 129 Output
Q21 128 Output
Q22 127 Output
Q23 126 Output
123 Output
Q24
Q25 122 Output
Q26 121 Output
Q27 120 Output
Q28 117 Output
Q29 116 Output
Q30 115 Output
Output
Q31 114
Q32 111 Output
Q33 110 Output
Q34 109 Output
Q35 108 Output
DE 19 Output
HSYNC 20 Output
VSYNC 21 Output
EVNODD 22 Output
ODCK 5 Output
Description
36-Bit Output Pixel Data Bus. Q35:0 is highly configurable using the
VDD_CONFIG register. It supports a wide array of output formats, including
multiple RBG and YCbCr bus formats. Using the appropriate bits in the PD
register, the output drivers can be put into a high impedance (tri-state) mode.
A weak, internal pull-down device brings each output to ground.
Data Enable.
Horizontal Sync Output.
Vertical Sync Output.
Indicates Even or Odd Field for Interlaced Formats.
Output Data Clock.
TX-SR806/SA806