Table of Contents
Advertisement
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -47
Q8200: FLI30336 (Video Processor, TORINO)
TERMINAL DESCRIPTION(5/10)
OCM External ROM/SRAM Control Signal
Pin name
ROM_CSn
OCM_CS0n
OCM_CS1n
OCM_CS2n
OCM_REn
OCM_WEn
OCM Peripherals
Pin name
OCM_INT1
OCM_INT2
OCM_UDO_0
OCM_UDI_0
OCM_UDO_1
OCM_UDI_1
IR0
PWM0
PWM1
PWM2
OCM_TIMER1
MSTR0_SDA
MSTR0_SCL
MSTR1_SDA
MSTR1_SCL
MSTR2_SDA
MSTR2_SCL
VGA0_SDA
VGA0_SCL
VGA1_SDA
VGA1_SCL
SLAVE_SDA
SLAVE_SCL
System
Pin name
RESETn
N/C
Power Panel Control
Pin name
PPWR
PBIAS
Pin#
I/O
Description
AD24
O
Chip select output signal to external ROM.
AD25
I/O
Chip select output signal to external peripheral.
AD26
I/O
Chip select output signal to external peripheral.
AC24
I/O
Chip select output signal to external peripheral.
AC25
O
Read enable output signal to enable external device to drive data pin(ball).
AC26
O
Write enable output signal to enable writing external devices.
Pin#
I/O
Description
W23
I/O
Interrupt #1 input for generating system interrupt to OCM. Level sensitive.
Y24
I/O
Interrupt #2 input for generating system interrupt to OCM. Edge sensitive.
W26
I/O
OCM UART '0' data output.
W25
I/O
OCM UART '0' data input.
B2
I/O
OCM UART '1' data output.
B3
I/O
OCM UART '1' data input.
AB24
I/O
Input to IR decoder.
V24
I/O
Pulse width modulator '0' output.
U23
I/O
Pulse width modulator '1' output.
U24
I/O
Pulse width modulator '2' output.
W24
I/O
Timer In: used as clock or clock enable input to OCMTIMER1.
AA23
I/O
Two wire serial master - Bus '0' data.
AA24
I/O
Two wire serial master - Bus '0' data.
A2
I/O
Two wire serial master - Bus '1' data.
A3
I/O
Two wire serial master - Bus '1' data.
AB25
I/O
Two wire serial master - Bus '2' data.
AB26
I/O
Two wire serial master - Bus '2' data.
AA25
I/O
Can be configured as data for two wire serial In-Circuit JTAG debugger.
AA26
I/O
Can be configured as clock for two wire serial In-Circuit JTAG debugger.
Y25
I/O
Can be configured as data for two wire serial In-Circuit JTAG debugger.
Y26
I/O
Can be configured as clock for two wire serial In-Circuit JTAG debugger.
V25
I/O
Two wire slave serial data.
V26
I/O
Two wire slave serial clock.
Pin#
I/O
Description
AD9
I/O
Hard Reset, active low input.
A1
I/O
No connect.
Pin#
I/O
Description
U25
O
Panel Power Control output controlled by Panel Power On Sequencer.
U26
O
Panel Bias Control controlled by Panel Power On Sequencer.
TX-SR806/SA806
Hide quick links:
Advertisement
Table of Contents
